Patents by Inventor Xiaoying Li

Xiaoying Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12026384
    Abstract: Aspects of a storage device including a memory and a controller are provided. In certain aspects, the controller may determine that data stored on a first block satisfies a threshold data-error condition, the data comprising invalid data and valid data. For example, the first block may have a high ratio of valid data to invalid data that satisfies or exceeds a threshold value. In certain aspects, the controller may determine a close block boundary associated with the first block, wherein the close block boundary is configured to bifurcate the first block into a first portion and a second portion, wherein the first portion comprises the data. For example, the controller may determine a boundary defined by a data length, an indirection mapping unit, a physical program boundary, etc.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: July 2, 2024
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ji-Hyun In, Yosief Ataklti, Aajna Karki, Hongmei Xie, Xiaoying Li
  • Publication number: 20240168683
    Abstract: A data storage device for providing zone management optimization may include memories including staging memory areas (e.g., single level cells) and destination memory areas (e.g., quad-level cells). The destination memory areas may include memory regions (e.g., zones). A controller may be configured to receive data from a host system, write the data initially to the staging memory areas, receive a region full indication for a first memory region. In response to receiving the region full indication, the controller may add a first entry corresponding to the first memory region to a double linked list. The controller may select, using a region selection randomization method, a second entry corresponding to a second memory region, and folds a second data to the second memory region. The first data may be associated with the first memory region and the second data may be associated with the second memory region.
    Type: Application
    Filed: July 13, 2023
    Publication date: May 23, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventor: Xiaoying LI
  • Publication number: 20240168684
    Abstract: A data storage device for providing efficient deallocation and reset of zones may include a host interface for coupling the data storage device to a host system. The data storage device may also include a controller. The controller may be configured to receive a format or reset zone command from a host system. The controller may also be configured to, in response to receiving the format or reset zone command, extract a time limit from the format or reset command. The controller may also be configured to, within the time limit: set a bitmap for a plurality of memory regions; and perform deallocation or reset of zones of at least a portion of the plurality of memory regions, according to the bitmap. The controller may also return a command completion to the host system.
    Type: Application
    Filed: July 13, 2023
    Publication date: May 23, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Xiaoying LI, Hyuk-Il KWON
  • Publication number: 20240069773
    Abstract: Aspects of a storage device including a memory and a controller are provided. In certain aspects, the controller may determine that data stored on a first block satisfies a threshold data-error condition, the data comprising invalid data and valid data. For example, the first block may have a high ratio of valid data to invalid data that satisfies or exceeds a threshold value. In certain aspects, the controller may determine a close block boundary associated with the first block, wherein the close block boundary is configured to bifurcate the first block into a first portion and a second portion, wherein the first portion comprises the data. For example, the controller may determine a boundary defined by a data length, an indirection mapping unit, a physical program boundary, etc.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Inventors: Ji-Hyun IN, Yosief ATAKLTI, Aajna KARKI, Hongmei XIE, Xiaoying LI
  • Publication number: 20240038776
    Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a middle display region, and first and second peripheral display regions arranged at two opposite sides of the middle display region respectively. Each pixel unit includes at least two sub-pixels in different colors and having a rectangular shape including long and short sides. In the middle display region and at least one of the first and second peripheral display regions, the sub-pixels in each pixel unit are sequentially arranged along a short side extension direction, extension directions of the first and second peripheral display regions are perpendicular to the short side extension direction in the middle display region, and the short side extension direction in at least one of the first and second peripheral display regions is perpendicular to the short side extension direction in the middle display region.
    Type: Application
    Filed: April 30, 2021
    Publication date: February 1, 2024
    Inventors: Jingjing JIANG, Xiaona LIU, Yu MA, Weitao CHEN, Xibin SHAO, Yan YAN, Wei CAO, Xiaoying LI
  • Patent number: 11876102
    Abstract: The present disclosure provides a display substrate, a display panel and a display apparatus, belonging to the field of display technology. The display substrate includes a base, a plurality of common electrodes and a plurality of common electrode lines, the common electrodes are distributed on the base in an array, the common electrode lines extend along a row direction, and each common electrode line is connected to a corresponding row of common electrodes. The common electrode line is connected to the common electrode through a conductive connection portion, and the conductive connection portion includes conductive structures stacked on top of one another in a plurality of layers. The display substrate can reduce the resistance between the common electrode and the common electrode line, thereby reducing the voltage difference between the common electrodes in the display substrate and improving the uniformity of the common voltage therein.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: January 16, 2024
    Assignees: Beijing BOE Display Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xue Wang, Xiao Wang, Yan Yan, Tingting Wang, Yaya Qi, Xiaoying Li, Zhiqiang Ma
  • Publication number: 20240015939
    Abstract: The present disclosure provides a display substrate, including: a display area and a bonding area positioned on a side of the display area, the bonding area includes a plurality of bonding sub-areas arranged at intervals, the bonding sub-areas are arranged along a direction in which an edge of the display area extends and configured for bonding a chip-on-film, where a first antistatic layer is further arranged on the bonding area, at least a part of the first antistatic layer is positioned between adjacent ones of the bonding sub-areas, and the first antistatic layer is electrically coupled to a reference signal terminal. The present disclosure further provides a display device.
    Type: Application
    Filed: September 25, 2023
    Publication date: January 11, 2024
    Inventors: Yaya QI, Dianzheng DONG, Yan YAN, Xiao WANG, Xue WANG, Tingting WANG, Xiaoying LI, Zhiqiang MA
  • Patent number: 11805630
    Abstract: The present disclosure provides a display substrate, including: a display area and a bonding area positioned on a side of the display area, the bonding area includes a plurality of bonding sub-areas arranged at intervals, the bonding sub-areas are arranged along a direction in which an edge of the display area extends and configured for bonding a chip-on-film, where a first antistatic layer is further arranged on the bonding area, at least a part of the first antistatic layer is positioned between adjacent ones of the bonding sub-areas, and the first antistatic layer is electrically coupled to a reference signal terminal. The present disclosure further provides a display device.
    Type: Grant
    Filed: February 7, 2021
    Date of Patent: October 31, 2023
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yaya Qi, Dianzheng Dong, Yan Yan, Xiao Wang, Xue Wang, Tingting Wang, Xiaoying Li, Zhiqiang Ma
  • Publication number: 20230154935
    Abstract: The present disclosure provides a display substrate, a display panel and a display apparatus, belonging to the field of display technology. The display substrate includes a base, a plurality of common electrodes and a plurality of common electrode lines, the common electrodes are distributed on the base in an array, the common electrode lines extend along a row direction, and each common electrode line is connected to a corresponding row of common electrodes. The common electrode line is connected to the common electrode through a conductive connection portion, and the conductive connection portion includes conductive structures stacked on top of one another in a plurality of layers. The display substrate can reduce the resistance between the common electrode and the common electrode line, thereby reducing the voltage difference between the common electrodes in the display substrate and improving the uniformity of the common voltage therein.
    Type: Application
    Filed: January 19, 2023
    Publication date: May 18, 2023
    Inventors: Xue WANG, Xiao WANG, Yan YAN, Tingting WANG, Yaya QI, Xiaoying LI, Zhiqiang MA
  • Patent number: 11640260
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The data storage device supports zoned namespace. The controller is configured to maintain a zone timestamp table that includes a corresponding timestamp for each zone and add a timestamp to each garbage collection block of the memory device. The controller is further configured to scan a garbage collection block from a last physical block address (PBA) entry to a first PBA entry, determine a zone timestamp for the scanned PBA entry, and compare the zone timestamp to a timestamp of the garbage collection block. The controller is further configured to create and maintain a zone timestamp table and create and maintain a zone based defragmentation table.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: May 2, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Hongmei Xie, Aajna Karki, Xiaoying Li, Ji-Hyun In, Dhanunjaya Rao Gorrle
  • Patent number: 11609154
    Abstract: Disclosed in this invention is a flat-belt type VTEHIL test bench for commercial vehicles, including a main bench body and a bench test system. The main bench body is mounted inside a foundation and includes a main bench frame, a bench cover, front axle flat-belt assemblies and rear axle flat-belt assemblies. Each front axle flat-belt assembly is provided therein with a fixed plate, a rotary disc and a limiting mechanism. Each rear axle flat-belt assembly includes a flat belt and flat belt pulleys disposed both within the flat belt at opposing ends thereof. The foundation defines a sector-shaped mounting depression in which the main bench body is mounted, and an iron floor is arranged under the main bench body. This invention can better simulate actual driving surfaces and accommodate two-axle, three-axle, four-axle and other types of trucks or tractors.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: March 21, 2023
    Assignee: SHANGHAI DIGAUTO AUTOMOBILE TECHNOLOGY CO., LTD.
    Inventors: Jiming Lv, Xiaoying Li, Libo Dong, Guanglei Bai, Yu Qiu
  • Patent number: 11586088
    Abstract: The present disclosure provides a display substrate, a display panel and a display apparatus, belonging to the field of display technology. The display substrate includes a base, a plurality of common electrodes and a plurality of common electrode lines, the common electrodes are distributed on the base in an array, the common electrode lines extend along a row direction, and each common electrode line is connected to a corresponding row of common electrodes. The common electrode line is connected to the common electrode through a conductive connection portion, and the conductive connection portion includes conductive structures stacked on top of one another in a plurality of layers. The display substrate can reduce the resistance between the common electrode and the common electrode line, thereby reducing the voltage difference between the common electrodes in the display substrate and improving the uniformity of the common voltage therein.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: February 21, 2023
    Assignees: Beijing BOE Display Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xue Wang, Xiao Wang, Yan Yan, Tingting Wang, Yaya Qi, Xiaoying Li, Zhiqiang Ma
  • Patent number: 11543993
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The data storage device supports zoned namespace. The controller is configured to maintain a zone timestamp table that includes a corresponding timestamp for each zone and add a timestamp to each garbage collection block of the memory device. The controller is further configured to scan a garbage collection block from a last physical block address (PBA) entry to a first PBA entry, determine a zone timestamp for the scanned PBA entry, and compare the zone timestamp to a timestamp of the garbage collection block. The controller is further configured to create and maintain a zone timestamp table and create and maintain a zone based defragmentation table.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: January 3, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Hongmei Xie, Aajna Karki, Xiaoying Li, Ji-Hyun In, Dhanunjaya Rao Gorrle
  • Publication number: 20220404996
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The data storage device supports zoned namespace. The controller is configured to maintain a zone timestamp table that includes a corresponding timestamp for each zone and add a timestamp to each garbage collection block of the memory device. The controller is further configured to scan a garbage collection block from a last physical block address (PBA) entry to a first PBA entry, determine a zone timestamp for the scanned PBA entry, and compare the zone timestamp to a timestamp of the garbage collection block. The controller is further configured to create and maintain a zone timestamp table and create and maintain a zone based defragmentation table.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 22, 2022
    Inventors: Hongmei XIE, Aajna KARKI, Xiaoying LI, Ji-Hyun IN, Dhanunjaya Rao GORRLE
  • Publication number: 20220405001
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The data storage device supports zoned namespace. The controller is configured to maintain a zone timestamp table that includes a corresponding timestamp for each zone and add a timestamp to each garbage collection block of the memory device. The controller is further configured to scan a garbage collection block from a last physical block address (PBA) entry to a first PBA entry, determine a zone timestamp for the scanned PBA entry, and compare the zone timestamp to a timestamp of the garbage collection block. The controller is further configured to create and maintain a zone timestamp table and create and maintain a zone based defragmentation table.
    Type: Application
    Filed: July 21, 2022
    Publication date: December 22, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Hongmei XIE, Aajna KARKI, Xiaoying LI, Ji-Hyun IN, Dhanunjaya Rao GORRLE
  • Publication number: 20220346291
    Abstract: The present disclosure provides a display substrate, including: a display area and a bonding area positioned on a side of the display area, the bonding area includes a plurality of bonding sub-areas arranged at intervals, the bonding sub-areas are arranged along a direction in which an edge of the display area extends and configured for bonding a chip-on-film, where a first antistatic layer is further arranged on the bonding area, at least a part of the first antistatic layer is positioned between adjacent ones of the bonding sub-areas, and the first antistatic layer is electrically coupled to a reference signal terminal. The present disclosure further provides a display device.
    Type: Application
    Filed: February 7, 2021
    Publication date: October 27, 2022
    Inventors: Yaya QI, Dianzheng DONG, Yan YAN, Xiao WANG, Xue WANG, Tingting WANG, Xiaoying LI, Zhiqiang MA
  • Publication number: 20220187666
    Abstract: The present disclosure provides a display substrate, a display panel and a display apparatus, belonging to the field of display technology. The display substrate includes a base, a plurality of common electrodes and a plurality of common electrode lines, the common electrodes are distributed on the base in an array, the common electrode lines extend along a row direction, and each common electrode line is connected to a corresponding row of common electrodes. The common electrode line is connected to the common electrode through a conductive connection portion, and the conductive connection portion includes conductive structures stacked on top of one another in a plurality of layers. The display substrate can reduce the resistance between the common electrode and the common electrode line, thereby reducing the voltage difference between the common electrodes in the display substrate and improving the uniformity of the common voltage therein.
    Type: Application
    Filed: February 26, 2021
    Publication date: June 16, 2022
    Inventors: Xue WANG, Xiao WANG, Yan YAN, Tingting WANG, Yaya QI, Xiaoying LI, Zhiqiang MA
  • Patent number: D970089
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: November 15, 2022
    Inventor: Xiaoying Li
  • Patent number: D986121
    Type: Grant
    Filed: March 14, 2023
    Date of Patent: May 16, 2023
    Inventor: Xiaoying Li
  • Patent number: D1001405
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: October 10, 2023
    Assignee: Shenzhen Update Electronics Co., Ltd.
    Inventor: Xiaoying Li