Abstract: An artificial intelligence (AI) accelerator device may include a plurality of on-chip mini buffers that are associated with a processing element (PE) array. Each mini buffer is associated with a subset of rows or a subset of columns of the PE array. Partitioning an on-chip buffer of the AI accelerator device into the mini buffers described herein may reduce the size and complexity of the on-chip buffer. The reduced size of the on-chip buffer may reduce the wire routing complexity of the on-chip buffer, which may reduce latency and may reduce access energy for the AI accelerator device. This may increase the operating efficiency and/or may increase the performance of the AI accelerator device. Moreover, the mini buffers may increase the overall bandwidth that is available for the mini buffers to transfer data to and from the PE array.

Abstract: A memory circuit includes a first buffer configured to store a plurality of first data elements; a second buffer configured to store a plurality of second data elements; a controller configured to generate a control signal based on a layer type; an array comprising a plurality of processing elements (PEs), each of the PEs including a plurality of storage cells; and a data router configured to receive the control signal and determine whether to store, in the storage cells of each of the PEs, a corresponding one of the plurality of first data elements or corresponding ones of the plurality of second data elements based on the control signal.

Abstract: A compute-in-memory memory (CIM) system includes: in a first region of a semiconductor die, first components including memory cells correspondingly configured to store single bits, and arrays including multipliers and first bit-error detectors; first ones of the memory cells being arranged in corresponding first arrays and being configured to store first bits; second ones of the memory cells being arranged in corresponding second arrays and being configured to store parity bits corresponding to the first bits; and for first groups each of which including a corresponding one of the first arrays, the second arrays, the multipliers and the first bit-error detectors, the multiplier being configured to perform a multiplication of input bits and corresponding ones of the first bits, and the first bit-error detector being configured to perform a detection of a bit-error in the corresponding first bits based on the corresponding parity bits.

Abstract: A memory circuit includes an array, a first buffer, a second buffer, a fetch circuit, and a controller. The fetch circuit can be configured to fetch a first subset of a first data elements from the first buffer and temporarily store the first subset of the first data elements, during a first cycle to write the first subset of the first data elements to a first subset of a plurality of processing elements (PEs) arranged along a first one of rows in the array. The controller can be configured to control the fetch circuit to selectively limit fetching a second subset of the first data elements from the first buffer, during a second subsequent cycle to write a second subset of the first data elements to a second subset of the PEs arranged along a second one of the rows.

Abstract: The present disclosure provides a defect-detectable fiber fabric, including a plurality of bunches of fibers and a plurality of braided threads configured to respectively fix together fibers of each bunch of fibers. The plurality of braided threads include first braided threads each having a color different from a color of any of the plurality of bunches of fibers, and a respective distance between every two adjacent first braided threads is configured to make wrinkle defects that could be formed in fabric layers detectable. After the curing and molding, the positions of the defects and the layer(s) where the defects are formed can be determined according to the states of the first braided threads.

Abstract: An improved machine learning based method for authorizing the performance of a treatment, comprising the steps of: receiving a treatment authorization request, the treatment authorization request including a historical record of the person who will receive the treatment and treatment identifying information relating to the treatment; creating an extracted text of the historical record using optical character recognition on the historical record; determining whether to analyze authorization performance of the treatment using a machine learning authorization process, wherein the determination is based on treatment identifying information and whether treatment authorization guidelines exist for the identified treatment; in response to a determination to analyze authorization performance of the treatment using a machine learning authorization process: identifying authorization criteria for the treatment based on the treatment authorization guidelines, wherein the authorization criteria includes records data condi

Abstract: An artificial intelligence (AI) accelerator device may include a plurality of on-chip mini buffers that are associated with a processing element (PE) array. Each mini buffer is associated with a subset of rows or a subset of columns of the PE array. Partitioning an on-chip buffer of the AI accelerator device into the mini buffers described herein may reduce the size and complexity of the on-chip buffer. The reduced size of the on-chip buffer may reduce the wire routing complexity of the on-chip buffer, which may reduce latency and may reduce access energy for the AI accelerator device. This may increase the operating efficiency and/or may increase the performance of the AI accelerator device. Moreover, the mini buffers may increase the overall bandwidth that is available for the mini buffers to transfer data to and from the PE array.

Abstract: A method for managing an ECU on a vehicle, and an ECU and a computer-readable storage medium are disclosed. The method may include: monitoring a working state of at least one ECU on a vehicle (S201); and in response to detecting an abnormal ECU in an abnormal working state, sending a control instruction to the abnormal ECU, where the control instruction is configured to trigger the abnormal ECU to execute a corresponding restore action (S202).

Abstract: Systems and methods for performing document entity extraction are described herein. The method can include receiving an inference document and a target schema. The method can also include generating one or more document inputs from the inference document and one or more schema inputs from the target schema. The method can further include, for each combination of the document input and schema input, obtaining one or more extraction inputs by generating a respective extraction input based on the combination, providing the respective extraction input to the machine-learned model, and receiving a respective output of the machine-learned model based on the respective extraction. The method can also include validating the extracted entity data based on reference spatial locations and inference spatial locations and outputting the validated extracted entity data.

Abstract: A memory system, an operating method and a controller are provided. The memory system comprises a memory array and a controller. The memory array comprises a probing memory block and a plurality of memory blocks. The controller is configured to perform; write a probing data to the probing memory block; detect a strength of the probing data from the probing memory block to obtain an aging condition of the memory array; and control each memory block to be enabled or disabled according to the aging condition.

Abstract: Embodiments of the application provide a distress information sending method and system. By setting automatic switching of various communication means, a user may be rescued in time. The method includes a terminal device obtains first distress information, where the first distress information includes at least one of adverse sign information or positioning information of a user. The terminal device selects a first communication network from a plurality of communication networks in a preset sequence. When the terminal device can be connected to the rescue processing device by using the first communication network, the terminal device sends the first distress information to the rescue processing device by using the first communication network. Alternatively, when the terminal device cannot be connected to the rescue processing device by using the first communication network, the terminal device reselects a new first communication network from the plurality of communication networks in the preset sequence.

Abstract: A communication method, a communication system, and an electronic device are provided. In a communication process, the electronic device may control time ratios of the electronic device for transmitting a signal, intercepting a signal, and sleeping based on a working mode selected by a user, and establish communication connection with another electronic device in a different working mode by planning a working cycle of the electronic device.

Abstract: A bacterial capsular oligosaccharide derivative, a preparation method therefor, a pharmaceutical composition and a use thereof. The derivative is as shown in formula (I), and the substituent is described in detail in the description. The derivative has anti-inflammatory activity and can be used for treating sepsis.

Abstract: Systems and methods are provided for a neural network that includes a multiply accumulate (MAC) unit that is configured to receive an input vector weight matrix; multiply the input matrix by the input vector weight matrix, generating input vector partial sums; receive time-delayed hidden vectors and a hidden vector weight matrix; and multiply the time-delayed hidden vectors and the hidden vector weight matrix, which generates hidden vector partial sums. An accumulator may be coupled to the MAC unit and configured to accumulate and add the input vector partial sums and the hidden vector partial sums, generating full sum vectors. The neural network may generate the time-delayed hidden vectors based on the full sum vectors. The neural network may further include a first selection device coupled to the MAC unit that is configured to select between the input matrix and the time-delayed hidden vectors for reception at the MAC unit.

Abstract: The present disclosure provides an accelerator circuit, a semiconductor device, and a method for accelerating convolution in a convolutional neural network. The accelerator circuit includes a plurality of sub processing-element (PE) arrays, and each of the plurality of sub PE arrays includes a plurality of processing elements. The processing elements in each of the plurality of sub PE arrays implement a standard convolutional layer during a first configuration applied to the accelerator circuit, and implement a depth-wise convolutional layer during a second configuration applied to the accelerator circuit.

Abstract: A wakeup method includes: A first signal processing circuit performs monitoring at a first frequency; a second signal processing circuit performs monitoring at a second frequency, where the second frequency is different from the first frequency; the second signal processing circuit receives a wakeup signal at the second frequency, where a bandwidth of the wakeup signal is less than a first value, the wakeup signal is transmitted by a first electronic device at a plurality of transmit frequencies or at a bandwidth greater than a second value, and the second value is greater than the first value; the first signal processing circuit performs monitoring at the second frequency; the second signal processing circuit performs monitoring at a third frequency, where the third frequency is different from both the first frequency and the second frequency; and the first signal processing circuit receives the wakeup signal at the second frequency.

Abstract: Syringe assemblies are provided including a partially pre-filled syringe barrel and a plunger rod that incorporates one or more retention elements on the plunger rod that prevents solution from entering a non-sterile area of the syringe when the plunger rod is pulled back. Methods to manufacture a sterilized partially-filled pre-fill syringe assembly are also disclosed.

Abstract: Disclosed are a fully human broad-spectrum neutralizing antibody against coronavirus, and the use thereof. Specifically disclosed are a fully human monoclonal antibody against an S2 region of coronavirus S protein, a nucleic acid sequence encoding the antibody, and a preparation method therefor. The antibody can effectively bind to and neutralize a variety of coronaviruses in a broad spectrum manner, and can be used for preventing and treating diseases related to coronavirus infection, such as SARS-CoV-2. Further disclosed is the potential use thereof in vaccine design.

Abstract: An artificial intelligence (AI) accelerator device may include a plurality of on-chip mini buffers that are associated with a processing element (PE) array. Each mini buffer is associated with a subset of rows or a subset of columns of the PE array. Partitioning an on-chip buffer of the AI accelerator device into the mini buffers described herein may reduce the size and complexity of the on-chip buffer. The reduced size of the on-chip buffer may reduce the wire routing complexity of the on-chip buffer, which may reduce latency and may reduce access energy for the AI accelerator device. This may increase the operating efficiency and/or may increase the performance of the AI accelerator device. Moreover, the mini buffers may increase the overall bandwidth that is available for the mini buffers to transfer data to and from the PE array.

Abstract: A circuit includes a data buffer configured to sequentially output first and second pluralities of bits, a plurality of memory macros having a total number, and a distribution network coupled between the data buffer and the plurality of memory macros. The distribution network separates the first plurality of bits into the total number of first subsets, and outputs each first subset to a corresponding memory macro, and either outputs an entirety of the second plurality of bits to each memory macro, or separates the second plurality of bits into a number of second subsets less than or equal to the total number, and outputs each second subset to one or more corresponding memory macros. Each memory macro outputs a product of the corresponding first subset and the one of the entirety of the second plurality of bits or the corresponding second subset of the second plurality of bits.