Patents by Inventor XIAOYUAN YU

XIAOYUAN YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12234617
    Abstract: The provided is a construction method for a flood storage area ecological wetland oriented to multi-target collaborative promotion. The construction method includes: I. carrying out ecological wetland construction on a flood storage area by taking promotion of agricultural production as a goal; II. according to a water purification target of the flood storage area of the ecological wetland and a current pollution condition in the flood storage area, constructing the ecological wetland based on improvement of the water purification target when the flood storage area does not reach the water purification target at present; and III, in order to improve the biodiversity, carrying out the following ecological wetland construction on the flood storage area. In the method, agricultural production, water purification and biodiversity improvement of the flood storage area are comprehensively considered. The method is the most effective way for multi-target collaborative promotion of the flood storage area.
    Type: Grant
    Filed: August 22, 2024
    Date of Patent: February 25, 2025
    Assignees: ANHUI SURVEY & DESIGN INSTITUTE OF WATER RESOURCES & HYDROPOWER CO., LTD., CHANGJIANG WATER RESOURCES PROTECTION INSTITUTE
    Inventors: Zhiyuan Cheng, Bo Jiang, Tao Li, Fengchan Zhang, Ting Yu, Xiaoyuan Wang, Zhenxin Li, Santao Xie, Siji Wang, Junfeng Li, Xinyi Zhang
  • Publication number: 20240264812
    Abstract: An application page development method includes a static page of a target application being first obtained, and then an application page including an interaction function corresponding to interaction description information being generated based on the interaction description information input by a user and the static page. In other words, the application page has a function of interacting with the user.
    Type: Application
    Filed: March 22, 2024
    Publication date: August 8, 2024
    Inventors: Zhiyu Ding, Zhaosong Huang, Xinxin Huang, Zhiyi Chen, Xiaofeng Deng, Minglei Li, Xiaoyuan Yu, Jing Yuan
  • Publication number: 20240202535
    Abstract: An artificial intelligence (AI) model training method is provided, including: determining a to-be-trained first model and a to-be-trained second model, where the first model and the second model are two heterogeneous AI models; inputting training data into the first model and the second model, to obtain a first output obtained by performing inference on the training data by the first model and a second output obtained by performing inference on the training data by the second model; and iteratively updating a model parameter of the first model by using the second output as a supervision signal of the first model and with reference to the first output, until the first model meets a first preset condition.
    Type: Application
    Filed: February 23, 2024
    Publication date: June 20, 2024
    Inventors: Bei TONG, Xiaoyuan YU
  • Publication number: 20240119130
    Abstract: A front-end device is configured to capture a light point image of an authenticatee and send the light point image to the back-end device, where the light point image is an image captured from the authenticatee under irradiation of multi-light points, and the light point image includes a face of the authenticatee. The back-end device of the authentication system is configured to perform face anti-spoofing detection on the authenticatee based on the received light point image to obtain an authentication result.
    Type: Application
    Filed: June 22, 2023
    Publication date: April 11, 2024
    Inventors: Ziwen HU, Anping LI, Xiaoyuan YU, Pu CHEN
  • Publication number: 20230298348
    Abstract: This disclosure relates to a clothing standardization detection method. In an example method, a clothing standardization detection apparatus obtains a video frame sub-image and a reference sub-image. The video frame sub-image includes an image of a first wear style of a target part of the target object in the first scenario, and the reference includes an image of a standard wear style of a target part of the reference object in the first scenario. Then, the video frame sub-image and the reference sub-image are processed by using a target model, to obtain a first processing result. The target model is a trained artificial intelligence AI model, and the first processing result indicates a similarity between the first wear style of the target part of the target object and the standard wear style of the target part of the reference object.
    Type: Application
    Filed: May 23, 2023
    Publication date: September 21, 2023
    Inventors: Ruizhi LU, Yi XIE, Xiaoyuan YU, Pu CHEN
  • Patent number: 10140128
    Abstract: A parallelized multiple dispatch ordered queue including an ordered queue, qualify logic, ordered select logic, and dispatch logic. The ordered queue stores candidates in order from oldest to youngest into multiple entries. The ordered queue is divided into N groups in which an i'th group includes every i'th entry of every N entries of the ordered queue, wherein i is an integer less than or equal to N. The qualify logic determines whether any candidate is ready to be dispatched. The ordered select logic respectively determines the oldest candidate in each group that is ready to be dispatched. The dispatch logic dispatches the oldest ready candidates in parallel. The shift logic shifts the stored candidates in the ordered queue to fill any vacant entries between remaining ones of the stored candidates without changing an order of the remaining ones of the stored candidates in the ordered queue. The ordered queue may have any size or depth and N is any suitable integer determining the number of candidates (e.g.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: November 27, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Qianli Di, Jianbin Wang, Weili Li, Xiaoyuan Yu, Xin Yu Gao
  • Patent number: 9928070
    Abstract: A microprocessor with a fused reservation stations (RS) structure including a primary RS, a secondary RS, and a bypass system. The primary RS has an input for receiving issued instructions, has a push output for pushing the issued instructions to the secondary RS, and has at least one bypass output for dispatching issued instructions that are ready for dispatch. The secondary RS has an input coupled to the push output of the primary RS and has at least one dispatch output. The bypass system selects between the bypass output of the primary RS and at least one dispatch output of the secondary RS for dispatching selected issued instructions. The primary and secondary RS may each be selected from different RS structure types. A unify RS provides a suitable primary RS, and the secondary RS may include multiple queues. The bypass output enables direct dispatch from the primary RS.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: March 27, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD
    Inventors: Qianli Di, Xiaoyuan Yu
  • Patent number: 9823933
    Abstract: A reissue instruction parking system for a microprocessor including a reservation stations module that dispatches instructions for execution and a reorder buffer that reissues instructions to the reservation stations module during a reissue state, in which the reissue instruction parking system includes at least one first pipeline stage and at least one second pipeline stage, in which the first pipeline stages provide a first reissue instruction from a reissue data path to the reservation stations module during the reissue state and that parks the first reissue instruction once the reservation stations module is determined to be full, and in which the second pipeline stages select a pointer to the reorder buffer which provides a corresponding first reissue instruction onto the reissue data path, in which the second pipeline stages are placed into a hold state when a second full signal is asserted.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: November 21, 2017
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Penghao Zou, Mengchen Yang, Jianbin Wang, Xiaoyuan Yu, Xin Yu Gao
  • Publication number: 20170090934
    Abstract: A microprocessor with a fused reservation stations (RS) structure including a primary RS, a secondary RS, and a bypass system. The primary RS has an input for receiving issued instructions, has a push output for pushing the issued instructions to the secondary RS, and has at least one bypass output for dispatching issued instructions that are ready for dispatch. The secondary RS has an input coupled to the push output of the primary RS and has at least one dispatch output. The bypass system selects between the bypass output of the primary RS and at least one dispatch output of the secondary RS for dispatching selected issued instructions. The primary and secondary RS may each be selected from different RS structure types. A unify RS provides a suitable primary RS, and the secondary RS may include multiple queues. The bypass output enables direct dispatch from the primary RS.
    Type: Application
    Filed: October 14, 2015
    Publication date: March 30, 2017
    Inventors: QIANLI DI, XIAOYUAN YU
  • Publication number: 20160266906
    Abstract: A reissue instruction parking system for a microprocessor including a reservation stations module that dispatches instructions for execution and a reorder buffer that reissues instructions to the reservation stations module during a reissue state, in which the reissue instruction parking system includes at least one first pipeline stage and at least one second pipeline stage, in which the first pipeline stages provide a first reissue instruction from a reissue data path to the reservation stations module during the reissue state and that parks the first reissue instruction once the reservation stations module is determined to be full, and in which the second pipeline stages select a pointer to the reorder buffer which provides a corresponding first reissue instruction onto the reissue data path, in which the second pipeline stages are placed into a hold state when a second full signal is asserted.
    Type: Application
    Filed: March 16, 2015
    Publication date: September 15, 2016
    Inventors: PENGHAO ZOU, MENGCHEN YANG, JIANBIN WANG, XIAOYUAN YU, XIN YU GAO
  • Publication number: 20160259648
    Abstract: A parallelized multiple dispatch ordered queue including an ordered queue, qualify logic, ordered select logic, and dispatch logic. The ordered queue stores candidates in order from oldest to youngest into multiple entries. The ordered queue is divided into N groups in which an i'th group includes every i'th entry of every N entries of the ordered queue, wherein i is an integer less than or equal to N. The qualify logic determines whether any candidate is ready to be dispatched. The ordered select logic respectively determines the oldest candidate in each group that is ready to be dispatched. The dispatch logic dispatches the oldest ready candidates in parallel. The shift logic shifts the stored candidates in the ordered queue to fill any vacant entries between remaining ones of the stored candidates without changing an order of the remaining ones of the stored candidates in the ordered queue. The ordered queue may have any size or depth and N is any suitable integer determining the number of candidates (e.g.
    Type: Application
    Filed: March 10, 2015
    Publication date: September 8, 2016
    Inventors: QIANLI DI, JIANBIN WANG, WEILI LI, XIAOYUAN YU, XIN YU GAO