Abstract: Provided are three-dimensional forming method and system. The method includes: controlling, by acoustic wave, bio-ink in acoustic resonant cavity to form cell cluster pattern M1; performing controllable photocuring on pre-curing position of the cell cluster pattern M1, to obtain cured formed structure; transferring the cured formed structure; controlling, by acoustic wave, the bio-ink in the acoustic resonant cavity to form cell cluster pattern M2, and adjusting the position, in the bio-ink, of the cured formed structure, such that the position is accurately joined with pre-curing position of the cell cluster pattern M2; performing controllable photocuring on the pre-curing position of the cell cluster pattern M2, to obtain cured formed structure; and circularly executing steps 3-5 a preset number of times, to obtain the three-dimensional tissue structure.

Abstract: A chip package structure includes a glass substrate, a routing layer, and a plurality of dies. A first surface of the glass substrate has solder joints and a second surface of the glass substrate has substrate solder balls. The routing layer is located in the glass substrate, and the solder joints are electrically connected to the substrate solder balls by using the routing layer. Each die has chip solder balls, is located on the first surface of the glass substrate, and the solder joints are bonded to the chip solder balls. The embodiments can improve connection reliability between the die and the glass substrate and can reduce a signal transmission loss.

Abstract: This application discloses an optical module housing and a manufacturing method thereof, an optical module, and an optical communication device. The optical module housing includes a housing body and a plating layer, where the plating layer is located on a surface of the housing body, a roughness Ra of the plating layer at least in a contact area does not exceed 0.6 ?m, and the contact area is an area that is of the optical module housing and that is configured to be in contact with a heat sink. According to this application, the roughness Ra of the plating layer in the contact area is set not to exceed 0.6 ?m, so that when the optical module is connected to an optical module connector, a gap between the contact area of the optical module housing and the heat sink is smaller.

Abstract: Provided are three-dimensional forming method and system. The method includes: controlling, by acoustic wave, bio-ink in acoustic resonant cavity to form cell cluster pattern M1; performing controllable photocuring on pre-curing position of the cell cluster pattern M1, to obtain cured formed structure; transferring the cured formed structure; controlling, by acoustic wave, the bio-ink in the acoustic resonant cavity to form cell cluster pattern M2, and adjusting the position, in the bio-ink, of the cured formed structure, such that the position is accurately joined with pre-curing position of the cell cluster pattern M2; performing controllable photocuring on the pre-curing position of the cell cluster pattern M2, to obtain cured formed structure; and circularly executing steps 3-5 a preset number of times, to obtain the three-dimensional tissue structure.

Abstract: An optical phased board includes a plurality of optical waveguide layers and a plurality of isolation layers. Each optical waveguide layer includes a plurality of optical waveguides, and the optical waveguides are arranged side by side. The optical waveguide layers and the isolation layers are arranged in a superimposed manner, and each isolation layer is located between two adjacent optical waveguide layers. The optical phased board includes a two-dimensional optical waveguide array to perform two-dimensional beam scanning.

Abstract: Embodiments of this application provide a chip and a manufacturing method thereof, and an electronic device, and belong to the field of chip heat dissipation technologies. The chip includes a die and a thermal conductive sheet. An active surface of the die is connected to the thermal conductive sheet by using a first bonding layer. Heat generated at a part with a relatively high temperature on the active surface of the die can be quickly conducted and dispersed by using the thermal conductive sheet, so that temperatures on the active surface are evenly distributed to avoid an excessively high local temperature of the chip, thereby preventing running of the chip from being affected.

Abstract: Embodiments of the application provide a vertical interconnection structure and a manufacturing method thereof, a packaged chip, and a chip packaging method. Conductive pillars are formed on a first surface of a substrate. A first insulated support layer wrapping the conductive pillars is formed on the first surface of the substrate. The conductive pillars are located in the first insulated support layer. An upper surface of the conductive pillar that is away from the substrate is not covered by the first insulated support layer. Then the substrate is removed.

Abstract: A chip package structure includes a glass substrate, a routing layer, and a plurality of dies. A first surface of the glass substrate has solder joints and a second surface of the glass substrate has substrate solder balls. The routing layer is located in the glass substrate, and the solder joints are electrically connected to the substrate solder balls by using the routing layer. Each die has chip solder balls, is located on the first surface of the glass substrate, and the solder joints are bonded to the chip solder balls. The embodiments can improve connection reliability between the die and the glass substrate and can reduce a signal transmission loss.

Abstract: A high dielectric constant composite material and method for preparing organic thin film transistor using the material as dielectric. The method includes: using sol-gel method, hydrolyzing terminal group-containing silane coupling agent to form functional terminal group-containing silica sol, cross-linked with organic polymer to form composite sol as material of dielectric of organic thin film transistor; forming film by solution method such as spin coating, dip coating, inkjet printing, 3D printing, etc., forming dielectric after curing; preparing semiconductor and electrode respectively to prepare organic thin film transistor device, which, based on composite dielectric material, has mobility of 5 cm2/V·s, exceeding that of using SiO2, having low threshold voltage and no hysteresis effect. Compared with traditional processes like SiO2 thermal oxidation, above method has advantages of simple process, low cost, suitable for large-area preparation, with great market application value.

Abstract: Embodiments of this application provide a chip and a manufacturing method thereof, and an electronic device, and belong to the field of chip heat dissipation technologies. The chip includes a die and a thermal conductive sheet. An active surface of the die is connected to the thermal conductive sheet by using a first bonding layer. Heat generated at a part with a relatively high temperature on the active surface of the die can be quickly conducted and dispersed by using the thermal conductive sheet, so that temperatures on the active surface are evenly distributed to avoid an excessively high local temperature of the chip, thereby preventing running of the chip from being affected.

Abstract: Embodiments of the application provide a vertical interconnection structure and a manufacturing method thereof, a packaged chip, and a chip packaging method. Conductive pillars are formed on a first surface of a substrate. A first insulated support layer wrapping the conductive pillars is formed on the first surface of the substrate. The conductive pillars are located in the first insulated support layer. An upper surface of the conductive pillar that is away from the substrate is not covered by the first insulated support layer. Then the substrate is removed.

Abstract: A high dielectric constant composite material and method for preparing organic thin film transistor using the material as dielectric. The method includes: using sol-gel method, hydrolyzing terminal group-containing silane coupling agent to form functional terminal group-containing silica sol, cross-linked with organic polymer to form composite sol as material of dielectric of organic thin film transistor; forming film by solution method such as spin coating, dip coating, inkjet printing, 3D printing, etc., forming dielectric after curing; preparing semiconductor and electrode respectively to prepare organic thin film transistor device, which, based on composite dielectric material, has mobility of 5 cm2/V·s, exceeding that of using SiO2, having low threshold voltage and no hysteresis effect. Compared with traditional processes like SiO2 thermal oxidation, above method has advantages of simple process, low cost, suitable for large-area preparation, with great market application value.