Abstract: A system and method to inhibit the erasing of a portion of a sector of split gate flash memory cells while allowing the remainder of the sector to be erased is disclosed. The inhibiting is controlled by control logic that applies one or more bias voltages to the portion of the sector whose erasure is to be inhibited.

Abstract: A self-timer for a sense amplifier in a memory device is disclosed.

Abstract: A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.

Abstract: The invention comprises a non-volatile memory device with a sensing amplifier that includes a current mirror comprising a pair of resistors.

Abstract: A trimmable current reference generator for use in a sense amplifier is disclosed.

Abstract: A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.

Abstract: The disclosed embodiments comprise a flash memory device and a method of programming the device in a way that reduces degradation of the device compared to prior art methods.

Abstract: An improved sensing circuit is disclosed that utilizes a bit line in an unused memory array to provide reference values to compare against selected cells in another memory array. A circuit that can perform a self-test for identifying bit lines with leakage currents about an acceptable threshold also is disclosed.

Abstract: A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.

Abstract: A trimmable sense amplifier for use in a memory device is disclosed.

Abstract: A bitline regulator for use in a high speed flash memory system is disclosed. The bitline regulator is responsive to a set of trim bits that are generated by comparing the bias voltage of a bitline to a reference voltage.

Abstract: A non-volatile memory device with a current injection sensing amplifier is disclosed.

Abstract: A system and method to inhibit the erasing of a portion of a sector of split gate flash memory cells while allowing the remainder of the sector to be erased is disclosed. The inhibiting is controlled by control logic that applies one or more bias voltages to the portion of the sector whose erasure is to be inhibited.

Abstract: A bitline regulator for use in a high speed flash memory system is disclosed. The bitline regulator is responsive to a set of trim bits that are generated by comparing the bias voltage of a bitline to a reference voltage.

Abstract: A self-timer for a sense amplifier in a memory device is disclosed.

Abstract: A system and method for a digitally controlled delay-locked loop reference generator is disclosed.

Abstract: A non-volatile memory device with a sensing amplifier (10) that includes a current mirror comprising a pair of resistors (20,30) and an operational amplifier (40) is disclosed.

Abstract: A non-volatile memory device with a current injection sensing amplifier is disclosed.

Abstract: A trimmable current reference generator for use in a sense amplifier is disclosed

Abstract: A trimmable sense amplifier for use in a memory device is disclosed.