Patents by Inventor Xiawan Yang

Xiawan Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12334358
    Abstract: Exemplary processing methods may include depositing a boron-containing material or a silicon-and-boron-containing material on a substrate disposed within a processing region of a semiconductor processing chamber. The methods may include etching portions of the boron-containing material or the silicon-and-boron-containing material with a chlorine-containing precursor to form one or more features in the substrate. The methods may also include removing remaining portions of the boron-containing material or the silicon-and-boron-containing material from the substrate with a fluorine-containing precursor.
    Type: Grant
    Filed: July 18, 2021
    Date of Patent: June 17, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Takehito Koshizawa, Karthik Janakiraman, Rui Cheng, Krishna Nittala, Menghui Li, Ming-Yuan Chuang, Susumu Shinohara, Juan Guo, Xiawan Yang, Russell Chin Yee Teo, Zihui Li, Chia-Ling Kao, Qu Jin, Anchuan Wang
  • Publication number: 20250062131
    Abstract: Methods of semiconductor processing may include forming plasma effluents of a plurality of precursors (e.g., an etchant precursor, an oxygen-containing precursor, and a silicon-and-fluorine-containing precursor like silicon tetrafluoride). The plasma effluents may then contact a silicon-containing material and a mask material on a substrate in a processing region of a semiconductor processing chamber. The mask material may have one or more apertures therein that allow the plasma effluents access to the silicon-containing material. Contacting the silicon-containing material and the mask material with the plasma effluents may cause (i) etching the silicon-containing material with the plasma effluents to form and/or deepen one or more features in the silicon-containing material and (ii) simultaneously etching the mask material and depositing a silicon-and-oxygen-containing material on the mask material with the plasma effluents.
    Type: Application
    Filed: August 16, 2023
    Publication date: February 20, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Hanbyul Jin, Sangjun Park, Menghui Li, Xiawan Yang, Sunil Srinivasan, Meishen Liu, Andrew Butler, Qian Fu
  • Publication number: 20250054768
    Abstract: Exemplary semiconductor processing methods may include providing an oxygen-containing precursor and a sulfur-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. A layer of carbon-containing material may be disposed on the substrate. The methods may include forming plasma effluents of the oxygen-containing precursor and the sulfur-containing precursor. The methods may include contacting the substrate with the plasma effluents of the oxygen-containing precursor and the sulfur-containing precursor. The contacting may etch a feature in the layer of carbon-containing material. A chamber operating temperature may be maintained at less than or about 0° C.
    Type: Application
    Filed: August 11, 2023
    Publication date: February 13, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Jiajing Li, Mengjie Lyu, Menghui Li, Xiawan Yang, Olivier P. Joubert, Susumu Shinohara, Qian Fu
  • Publication number: 20250054770
    Abstract: Exemplary semiconductor processing methods may include providing a fluorine-containing precursor and a carbon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. A layer of oxygen-containing material may be disposed on the substrate. The methods may include forming plasma effluents of the fluorine-containing precursor and the carbon-containing precursor. The methods may include contacting the substrate with the plasma effluents of the fluorine-containing precursor and the carbon-containing precursor. The contacting may etch a feature in the layer of oxygen-containing material. A semiconductor processing chamber operating temperature may be maintained at less than or about 0° C. during the semiconductor processing method.
    Type: Application
    Filed: August 11, 2023
    Publication date: February 13, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Jiajing Li, Mengjie Lyu, Menghui Li, Xiawan Yang, Olivier P. Joubert, Susumu Shinohara, Qian Fu
  • Patent number: 11935751
    Abstract: Exemplary deposition methods may include delivering a boron-containing precursor and a nitrogen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor with the boron-containing precursor and the nitrogen-containing precursor. A flow rate ratio of the hydrogen-containing precursor to either of the boron-containing precursor or the nitrogen-containing precursor may be greater than or about 2:1. The methods may include forming a plasma of all precursors within the processing region of the semiconductor processing chamber. The methods may include depositing a boron-and-nitrogen material on a substrate disposed within the processing region of the semiconductor processing chamber.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: March 19, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Siyu Zhu, Chuanxi Yang, Hang Yu, Deenesh Padhi, Yeonju Kwak, Jeong Hwan Kim, Qian Fu, Xiawan Yang
  • Publication number: 20220384189
    Abstract: Exemplary deposition methods may include delivering a boron-containing precursor and a nitrogen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor with the boron-containing precursor and the nitrogen-containing precursor. A flow rate ratio of the hydrogen-containing precursor to either of the boron-containing precursor or the nitrogen-containing precursor may be greater than or about 2:1. The methods may include forming a plasma of all precursors within the processing region of the semiconductor processing chamber. The methods may include depositing a boron-and-nitrogen material on a substrate disposed within the processing region of the semiconductor processing chamber.
    Type: Application
    Filed: May 25, 2021
    Publication date: December 1, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Siyu Zhu, Chuanxi Yang, Hang Yu, Deenesh Padhi, Yeonju Kwak, Jeong Hwan Kim, Qian Fu, Xiawan Yang
  • Patent number: 11437230
    Abstract: Disclosed herein is a high throughput method for providing directional protection to a three dimensional feature on a substrate by forming a multi-layer amorphous carbon-containing coating with tunable conformality thereon. Forming the multi-layer amorphous carbon-containing coating with tunable conformality includes depositing a base layer onto a horizontal surface of the three dimensional features, and a second layer over the base layer and onto a first portion of a vertical or inclined surface of the three dimensional feature. The base layer includes a first material with a first sticking coefficient and the second layer includes a second material with a second sticking coefficient that is smaller than the first sticking coefficient. The first material includes no fluorine or less fluorine than the second material. Also disclosed herein is a method of manufacturing a three dimensional device as well as three dimensional devices.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: September 6, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Wei Wu, Feng Zhang, Xiawan Yang, Jinhan Choi, Anisul Haque Khan
  • Publication number: 20220020599
    Abstract: Exemplary processing methods may include depositing a boron-containing material or a silicon-and-boron-containing material on a substrate disposed within a processing region of a semiconductor processing chamber. The methods may include etching portions of the boron-containing material or the silicon-and-boron-containing material with a chlorine-containing precursor to form one or more features in the substrate. The methods may also include removing remaining portions of the boron-containing material or the silicon-and-boron-containing material from the substrate with a fluorine-containing precursor.
    Type: Application
    Filed: July 18, 2021
    Publication date: January 20, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Takehito Koshizawa, Karthik Janakiraman, Rui Cheng, Krishna Nittala, Menghui Li, Ming-Yuan Chuang, Susumu Shinohara, Juan Guo, Xiawan Yang, Russell Chin Yee Teo, Zihui Li, Chia-Ling Kao, Qu Jin, Anchuan Wang
  • Publication number: 20210313166
    Abstract: Disclosed herein is a high throughput method for providing directional protection to a three dimensional feature on a substrate by forming a multi-layer amorphous carbon-containing coating with tunable conformality thereon. Forming the multi-layer amorphous carbon-containing coating with tunable conformality includes depositing a base layer onto a horizontal surface of the three dimensional features, and a second layer over the base layer and onto a first portion of a vertical or inclined surface of the three dimensional feature. The base layer includes a first material with a first sticking coefficient and the second layer includes a second material with a second sticking coefficient that is smaller than the first sticking coefficient. The first material includes no fluorine or less fluorine than the second material. Also disclosed herein is a method of manufacturing a three dimensional device as well as three dimensional devices.
    Type: Application
    Filed: April 6, 2020
    Publication date: October 7, 2021
    Inventors: Wei Wu, Feng Zhang, Xiawan Yang, Jinhan Choi, Anisul Haque Khan
  • Patent number: 9305748
    Abstract: Etch rate distributions are captured at a succession of hardware tilt angles of the RF source power applicator relative to the workpiece and their non-uniformities computed, and the behavior is modeled as a non-uniformity function for each one of at least two plasma reactors. An offset ?? in tilt angle ? between the non-uniformity functions of the two plasma reactors is detected. The two plasma reactors are then matched by performing a hardware tilt in one of them through a tilt angle equal to the offset ??.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: April 5, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Gaurav Saraf, Xiawan Yang, Farid Abooameri, Wen Teh Chang, Anisul H. Khan, Bradley Scott Hersch
  • Patent number: 9184021
    Abstract: Etch rate distribution non-uniformities are predicted for a succession of hardware tilt angles of the RF source applicator relative to the workpiece, and the behavior is modeled as a non-uniformity function for each one of at least two plasma reactors. An offset ?? in tilt angle ? between the non-uniformity functions of the two plasma reactors is detected. The two reactors are then matched by performing a hardware tilt in one of them through a tilt angle equal to the offset ??.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: November 10, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Gaurav Saraf, Xiawan Yang, Farid Abooameri, Wen Teh Chang, Anisul H. Khan, Bradley Scott Hersch
  • Publication number: 20150096959
    Abstract: Etch rate distributions are captured at a succession of hardware tilt angles of the RF source power applicator relative to the workpiece and their non-uniformities computed, and the behavior is modeled as a non-uniformity function for each one of at least two plasma reactors. An offset ?? in tilt angle ? between the non-uniformity functions of the two plasma reactors is detected. The two plasma reactors are then matched by performing a hardware tilt in one of them through a tilt angle equal to the offset ??.
    Type: Application
    Filed: October 28, 2013
    Publication date: April 9, 2015
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Gaurav Saraf, Xiawan Yang, Farid Abooameri, Wen Teh Chang, Anisul H Khan, Bradley Scott Hersch
  • Publication number: 20150099314
    Abstract: Etch rate distribution non-uniformities are predicted for a succession of hardware tilt angles of the RF source applicator relative to the workpiece, and the behavior is modeled as a non-uniformity function for each one of at least two plasma reactors. An offset ?? in tilt angle ? between the non-uniformity functions of the two plasma reactors is detected. The two reactors are then matched by performing a hardware tilt in one of them through a tilt angle equal to the offset ??.
    Type: Application
    Filed: October 28, 2013
    Publication date: April 9, 2015
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Gaurav Saraf, Xiawan Yang, Farid Abooameri, Wen Teh Chang, Anisul H. Khan, Bradley Scott Hersch
  • Patent number: 8791506
    Abstract: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: July 29, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Ted Taylor, Xiawan Yang
  • Publication number: 20110316091
    Abstract: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.
    Type: Application
    Filed: September 2, 2011
    Publication date: December 29, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Ted Taylor, Xiawan Yang
  • Patent number: 8044479
    Abstract: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: October 25, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Ted Taylor, Xiawan Yang
  • Publication number: 20090200614
    Abstract: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.
    Type: Application
    Filed: April 15, 2009
    Publication date: August 13, 2009
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Ted Taylor, Xiawan Yang
  • Patent number: 7537994
    Abstract: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: May 26, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Ted Taylor, Xiawan Yang
  • Publication number: 20080048298
    Abstract: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.
    Type: Application
    Filed: August 28, 2006
    Publication date: February 28, 2008
    Inventors: Ted Taylor, Xiawan Yang
  • Publication number: 20060156983
    Abstract: Devices and methods for generating a low temperature atmospheric pressure plasma are disclosed. A method of generating a low temperature atmospheric pressure plasma that comprises coupling a high-frequency power supply to a tuning network that is connected to one or more electrodes, placing one or more non-conducting housings between the electrodes, flowing gas through the one or more housings, and striking and maintaining the plasma with the application of said high-frequency power is described. A technique for the surface treatment of materials with said low temperature atmospheric pressure plasma, including surface activation, cleaning, sterilization, etching and deposition of thin films is also disclosed.
    Type: Application
    Filed: September 14, 2005
    Publication date: July 20, 2006
    Applicant: Surfx Technologies LLC
    Inventors: Joel Penelon, Sylvain Motycka, Steve Babayan, Xiawan Yang