Abstract: Exemplary processing methods may include depositing a boron-containing material or a silicon-and-boron-containing material on a substrate disposed within a processing region of a semiconductor processing chamber. The methods may include etching portions of the boron-containing material or the silicon-and-boron-containing material with a chlorine-containing precursor to form one or more features in the substrate. The methods may also include removing remaining portions of the boron-containing material or the silicon-and-boron-containing material from the substrate with a fluorine-containing precursor.

Abstract: Methods of semiconductor processing may include forming plasma effluents of a plurality of precursors (e.g., an etchant precursor, an oxygen-containing precursor, and a silicon-and-fluorine-containing precursor like silicon tetrafluoride). The plasma effluents may then contact a silicon-containing material and a mask material on a substrate in a processing region of a semiconductor processing chamber. The mask material may have one or more apertures therein that allow the plasma effluents access to the silicon-containing material. Contacting the silicon-containing material and the mask material with the plasma effluents may cause (i) etching the silicon-containing material with the plasma effluents to form and/or deepen one or more features in the silicon-containing material and (ii) simultaneously etching the mask material and depositing a silicon-and-oxygen-containing material on the mask material with the plasma effluents.

Abstract: Exemplary semiconductor processing methods may include providing an oxygen-containing precursor and a sulfur-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. A layer of carbon-containing material may be disposed on the substrate. The methods may include forming plasma effluents of the oxygen-containing precursor and the sulfur-containing precursor. The methods may include contacting the substrate with the plasma effluents of the oxygen-containing precursor and the sulfur-containing precursor. The contacting may etch a feature in the layer of carbon-containing material. A chamber operating temperature may be maintained at less than or about 0° C.

Abstract: Exemplary semiconductor processing methods may include providing a fluorine-containing precursor and a carbon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. A layer of oxygen-containing material may be disposed on the substrate. The methods may include forming plasma effluents of the fluorine-containing precursor and the carbon-containing precursor. The methods may include contacting the substrate with the plasma effluents of the fluorine-containing precursor and the carbon-containing precursor. The contacting may etch a feature in the layer of oxygen-containing material. A semiconductor processing chamber operating temperature may be maintained at less than or about 0° C. during the semiconductor processing method.

Abstract: Exemplary deposition methods may include delivering a boron-containing precursor and a nitrogen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor with the boron-containing precursor and the nitrogen-containing precursor. A flow rate ratio of the hydrogen-containing precursor to either of the boron-containing precursor or the nitrogen-containing precursor may be greater than or about 2:1. The methods may include forming a plasma of all precursors within the processing region of the semiconductor processing chamber. The methods may include depositing a boron-and-nitrogen material on a substrate disposed within the processing region of the semiconductor processing chamber.

Abstract: Exemplary deposition methods may include delivering a boron-containing precursor and a nitrogen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor with the boron-containing precursor and the nitrogen-containing precursor. A flow rate ratio of the hydrogen-containing precursor to either of the boron-containing precursor or the nitrogen-containing precursor may be greater than or about 2:1. The methods may include forming a plasma of all precursors within the processing region of the semiconductor processing chamber. The methods may include depositing a boron-and-nitrogen material on a substrate disposed within the processing region of the semiconductor processing chamber.

Abstract: Disclosed herein is a high throughput method for providing directional protection to a three dimensional feature on a substrate by forming a multi-layer amorphous carbon-containing coating with tunable conformality thereon. Forming the multi-layer amorphous carbon-containing coating with tunable conformality includes depositing a base layer onto a horizontal surface of the three dimensional features, and a second layer over the base layer and onto a first portion of a vertical or inclined surface of the three dimensional feature. The base layer includes a first material with a first sticking coefficient and the second layer includes a second material with a second sticking coefficient that is smaller than the first sticking coefficient. The first material includes no fluorine or less fluorine than the second material. Also disclosed herein is a method of manufacturing a three dimensional device as well as three dimensional devices.

Abstract: Exemplary processing methods may include depositing a boron-containing material or a silicon-and-boron-containing material on a substrate disposed within a processing region of a semiconductor processing chamber. The methods may include etching portions of the boron-containing material or the silicon-and-boron-containing material with a chlorine-containing precursor to form one or more features in the substrate. The methods may also include removing remaining portions of the boron-containing material or the silicon-and-boron-containing material from the substrate with a fluorine-containing precursor.

Abstract: Disclosed herein is a high throughput method for providing directional protection to a three dimensional feature on a substrate by forming a multi-layer amorphous carbon-containing coating with tunable conformality thereon. Forming the multi-layer amorphous carbon-containing coating with tunable conformality includes depositing a base layer onto a horizontal surface of the three dimensional features, and a second layer over the base layer and onto a first portion of a vertical or inclined surface of the three dimensional feature. The base layer includes a first material with a first sticking coefficient and the second layer includes a second material with a second sticking coefficient that is smaller than the first sticking coefficient. The first material includes no fluorine or less fluorine than the second material. Also disclosed herein is a method of manufacturing a three dimensional device as well as three dimensional devices.

Abstract: Etch rate distributions are captured at a succession of hardware tilt angles of the RF source power applicator relative to the workpiece and their non-uniformities computed, and the behavior is modeled as a non-uniformity function for each one of at least two plasma reactors. An offset ?? in tilt angle ? between the non-uniformity functions of the two plasma reactors is detected. The two plasma reactors are then matched by performing a hardware tilt in one of them through a tilt angle equal to the offset ??.

Abstract: Etch rate distribution non-uniformities are predicted for a succession of hardware tilt angles of the RF source applicator relative to the workpiece, and the behavior is modeled as a non-uniformity function for each one of at least two plasma reactors. An offset ?? in tilt angle ? between the non-uniformity functions of the two plasma reactors is detected. The two reactors are then matched by performing a hardware tilt in one of them through a tilt angle equal to the offset ??.

Abstract: Etch rate distributions are captured at a succession of hardware tilt angles of the RF source power applicator relative to the workpiece and their non-uniformities computed, and the behavior is modeled as a non-uniformity function for each one of at least two plasma reactors. An offset ?? in tilt angle ? between the non-uniformity functions of the two plasma reactors is detected. The two plasma reactors are then matched by performing a hardware tilt in one of them through a tilt angle equal to the offset ??.

Abstract: Etch rate distribution non-uniformities are predicted for a succession of hardware tilt angles of the RF source applicator relative to the workpiece, and the behavior is modeled as a non-uniformity function for each one of at least two plasma reactors. An offset ?? in tilt angle ? between the non-uniformity functions of the two plasma reactors is detected. The two reactors are then matched by performing a hardware tilt in one of them through a tilt angle equal to the offset ??.

Abstract: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.

Abstract: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.

Abstract: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.

Abstract: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.

Abstract: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.

Abstract: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.

Abstract: Devices and methods for generating a low temperature atmospheric pressure plasma are disclosed. A method of generating a low temperature atmospheric pressure plasma that comprises coupling a high-frequency power supply to a tuning network that is connected to one or more electrodes, placing one or more non-conducting housings between the electrodes, flowing gas through the one or more housings, and striking and maintaining the plasma with the application of said high-frequency power is described. A technique for the surface treatment of materials with said low temperature atmospheric pressure plasma, including surface activation, cleaning, sterilization, etching and deposition of thin films is also disclosed.