Abstract: The embodiments of the present disclosure provide a drive control circuit, a control method thereof, and a display apparatus. The drive control circuit includes: a first control circuit configured to acquire image data, and output a first selection command signal according to the image data; and at least one second control circuit each coupled to at least one scan signal line in a display panel and coupled to the first control circuit. The at least one second control circuit is configured to receive the first selection command signal, determine, according to the first selection command signal, a target scan signal line from among scan signal lines in the display panel, and output a scan drive signal to the target scan signal line.

Abstract: A signal processing method, a display apparatus, an electronic device and a computer-readable storage medium are provided. The signal processing method for a display apparatus, the display apparatus includes a display substrate, the display substrate includes M rows and N columns of pixel units arranged in an array, and the signal processing method includes: acquiring display data of a frame of an image to be displayed, wherein the display data include P rows and Q columns of pixel data arranged in an array; generating P rows of gate scan signals corresponding to the P rows of pixel data; in a case where P is less than M, generating M-P rows of supplementary gate scan signals based on the P rows of gate scan signals; and driving the M rows of pixel units using the M rows of gate scan signals, respectively, P, Q, M and N are all positive integers.

Abstract: A front light source module is provided to include a side light source; a light guide layer with a light incident side opposite to the side light source in a first direction; and a first light adjusting layer, the first light adjusting layer and the light guide layer are stacked in a third direction, a portion of the first light adjusting layer away from the light guide layer is provided with micro-groove structures, each including: a first inclined surface and a second inclined surface opposite to each other in the first direction, the first inclined surface is configured to face the light incident sid, closer to the light incident side than the second inclined surface, angle ? between the first inclined surface and a plane where a surface of the first light adjusting layer away from the light guide layer is located is in a range from 26° to 42°.

Abstract: A display panel, a driving method for the display panel and a display device. The display panel includes a gate driving circuit, the gate driving circuit includes shift registers of a plurality of stages arranged in sequence, the shift registers of the plurality of stages arranged in sequence are combined into N groups of gate driving sub-circuits, and shift registers in the N groups of gate driving sub-circuits are cascaded, respectively; an m-th group of gate driving sub-circuits in the N groups of gate driving sub-circuits comprises a shift register of an m-th stage and a shift register of an (m+L*N)th stage that are cascaded, where m is an integer that is greater than or equal to 1 and less than or equal to N, L is an integer that is greater than or equal to 1, N is an even number that is greater than or equal to 2.

Abstract: A display substrate, including: a base substrate; a plurality of data lines on the base substrate; a first insulating layer on a side of the plurality of data lines away from the base substrate; a plurality of gate lines on a side of the first insulating layer away from the plurality of data lines, where extension directions of the gate and data lines are intersected; a second insulating layer on a side of the plurality of gate lines away from the first insulating layer; and a first electrode on a side of the second insulating layer away from the plurality of gate lines, where at least a portion of an orthographic projection of the first electrode on the base substrate is within an region surrounded by orthographic projections of two adjacent data lines on the base substrate and orthographic projections of two adjacent gate lines on the base substrate.

Abstract: At least one chip group and a group of first PLG wirings corresponding to each of the chip groups are disposed in a first bonding area, each of the chip groups includes at least two groups of chip units, each group of the chip units includes at least one gate drive chip, each group of the first PLG wirings includes a first wiring and at least one second wiring; power pins of any two adjacent gate drive chips are connected by the first wiring, each of the second wirings surrounds and passes through each of the gate drive chips, the first wirings connected with the power pin of the last gate drive chip in the previous group of the chip units and any of the second wirings, are parallelly connected with the power pin of the first gate drive chip in the next group of the chip units.

Abstract: A dual gate array substrate includes a plurality of groups of dual gate lines, a plurality of data lines, a plurality of pixel pairs and a plurality of common electrode lines, each common electrode line is arranged between two pixel units in a same pixel pair; and a layer where the common electrode line is located and a layer where a source/drain electrode of a thin film transistor is located are different layers and insulated from each other.

Abstract: A liquid crystal display panel includes a first and second base substrates, a liquid crystal layer and an optical compensation layer. In the liquid crystal layer, a first alignment film is configured to anchor a part, proximate to the first alignment film, of second liquid crystal molecules, and a second alignment film is configured to anchor a part, proximate to the second alignment film, of the second liquid crystal molecules. In the optical compensation layer, a third alignment film is configured to anchor first liquid crystal molecules proximate to the third alignment film. A direction of orthogonal projections of long axes of the first liquid crystal molecules is parallel to a direction of orthogonal projections of long axes of second liquid crystal molecules anchored by the first and second alignment films. Rubbing directions of the first alignment film, the second alignment film and the third alignment film are the same.

Abstract: The present invention relates to a touch display device, a drive control circuit for the touch display device, and a method for operating the touch display device. The touch display device includes a drive control circuit, the drive control circuit is configured to: in a display phase, provide a common voltage signal to a common electrode in a pixel circuit of the touch display device; in a touch phase, provide a touch drive signal to the common electrode, wherein a ratio of an average value of a high level and a low level of the touch drive signal to a value of the common voltage signal ranges from 0.8 to 1.2.

Abstract: There is provided a gate driving circuit, a display panel and a driving method of the gate driving circuit. The gate driving circuit includes multiple stages of shift registers. The multiple stages of shift registers comprise N first shift registers arranged alternately with N second shift registers. The N first shift registers are cascaded-coupled as N stages of first shift registers, and are configured to generate N first output signals under control of K first clock signals. The N second shift registers are cascaded-coupled as N stages of second shift registers, and are configured to generate N second output signals under a control of K second clock signals. K and N are both integers greater than 1, and K?N.

Abstract: A color coordinate calibration method, system, a processing device and a computer storage medium are provided. The method includes: displaying a test image on a display screen, testing the chromaticity of the display screen, and obtaining test color coordinates of a plurality of primary color lights; Detecting whether the test color coordinates of the plurality of primary color lights are within the standard color coordinate ranges of the plurality of primary color lights; when the test color coordinates of one or more primary color lights are not within the standard color coordinate ranges of the corresponding primary color lights, determining target color coordinates and target white balance color temperatures of a plurality of primary color lights, and adjusting the test color coordinates of one or more primary color lights to be within standard color coordinate ranges of the corresponding primary color lights.

Abstract: An oxide thin film transistor includes a gate electrode, and a first active layer structure and a second active layer structure arranged subsequently, the first active layer structure includes a first conductive connection portion and a second conductive connection portion arranged oppositely, the second active layer structure includes a third conductive connection portion and a fourth conductive connection portion arranged oppositely, and the second oxide semiconductor pattern respectively coupled to the third conductive connection portion and the fourth conductive connection portion, and an orthographic projection of the first oxide semiconductor pattern on the substrate and an orthographic projection of the second oxide semiconductor pattern on the substrate are both located within an orthographic projection of the gate electrode on the substrate, the second conductive connection portion is coupled to the third conductive connection portion.

Abstract: An array substrate includes a base substrate, pixel electrodes and common electrodes, first scan lines, second scan lines and data lines. The pixel electrode has first electrode strips disposed at intervals in a row direction. The common electrodes and the pixel electrodes are disposed on the same layer, and the common electrodes have second electrode strips disposed at intervals. The second electrode strips and the first electrode strips are alternatively arranged. The first scan line is located between two adjacent rows of pixel electrodes. The second scan line is located between two adjacent columns of pixel electrodes and is electrically connected to the first scan line, and the second scan line has a scan signal input terminal. The data line has a data signal input terminal. An orthographic projection of the data line on the base substrate intersects with a central region of the pixel electrode on the base substrate.

Abstract: The present disclosure provides a display panel driving method, a display panel and a display device, the method comprising: comprising alternately configure display time periods and touch time periods in one time frame, at least one touch time period being configured, and at least two display time periods being configured; sequentially scanning in each display time period a portion of gate lines in a display panel; and pausing in each touch time period the scanning of all gate lines, and performing touch recognition, wherein in a display time period adjacent to a touch time period, level compensation is performed on a gate line to be compensated, and the gate line to be compensated is at least one gate line that starts to scan in the display time period adjacent to the touch time period.

Abstract: An oxide thin film transistor includes a gate electrode, and a first active layer structure and a second active layer structure arranged subsequently, the first active layer structure includes a first conductive connection portion and a second conductive connection portion arranged oppositely, the second active layer structure includes a third conductive connection portion and a fourth conductive connection portion arranged oppositely, and the second oxide semiconductor pattern respectively coupled to the third conductive connection portion and the fourth conductive connection portion, and an orthographic projection of the first oxide semiconductor pattern on the substrate and an orthographic projection of the second oxide semiconductor pattern on the substrate are both located within an orthographic projection of the gate electrode on the substrate, the second conductive connection portion is coupled to the third conductive connection portion.

Abstract: A display device and a method for bonding the display device are provided. The display device includes a display panel and a plurality of chip on films. The plurality of chip on films are arranged along a first edge of the display panel, and are divided into a plurality of groups of chip on films, and each group of chip on films includes at least two chip on films, and is bonded to the display panel through a same anisotropic conductive film.

Abstract: There is provided a gate driving circuit comprising N first shift registers arranged alternately with N second shift registers. An input signal terminal of an n-th stage of first shift register is coupled to an output signal terminal of an (n?i)-th stage of first shift register, and a reset signal terminal of the n-th stage of first shift register is coupled to an output signal terminal of an (n+j)-th stage of first shift register. Input signal terminal and reset signal terminal of n-th stage of second shift register are coupled to output signal terminals of (n?i)-th and (n+j)-th stages of second shift registers respectively. K=6, i=3, and j=4. Reset signal terminals of (N?j+1)-th to N-th stages of first shift registers and reset signal terminals of (N?j+1)-th to N-th stages of second shift registers are configured to receive a total reset signal.

Abstract: A display substrate, including: a base substrate; a plurality of data lines on the base substrate; a first insulating layer on a side of the plurality of data lines away from the base substrate; a plurality of gate lines on a side of the first insulating layer away from the plurality of data lines, where extension directions of the gate and data lines are intersected; a second insulating layer on a side of the plurality of gate lines away from the first insulating layer; and a first electrode on a side of the second insulating layer away from the plurality of gate lines, where at least a portion of an orthographic projection of the first electrode on the base substrate is within an region surrounded by orthographic projections of two adjacent data lines on the base substrate and orthographic projections of two adjacent gate lines on the base substrate.

Abstract: A display panel and a display device are disclosed. The display panel includes a gate driving circuit, a plurality of clock signal lines, a timing controller and a plurality of anti-cross-row circuits; the timing controller is configured to provide a first clock signal; the plurality of anti-cross-row circuits are connected with the timing controller and the plurality of clock signal lines, and are configured to adjust the first clock signal provided by the timing controller to a second clock signal, and output the second clock signal to the plurality of clock signal lines, and a falling duration of a falling edge of the second clock signal is less than a falling duration of a falling edge of the first clock signal; and each of the plurality of anti-cross-row circuits comprises at least one resistor and at least one inductor.

Abstract: A display driving method and a display device are provided. The display driving method includes: scanning a plurality of subpixels arranged in an N?M array row by row or in multiple rows to turn on each row of scanned subpixels, so that the duration when two adjacent rows of subpixels are simultaneously in a turn-on state is greater than or equal to two times a unit scan time, the unit scan time being the time required for scanning one row of subpixels, and N and M both being integers greater than 1; and applying data signals to at least two rows of subpixels that are simultaneously in the turn-on state, so that the duration when data signals are applied to at least some rows of subpixels is greater than the unit scan time.