Patents by Inventor Xie Miao
Xie Miao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250103557Abstract: In a data processing method, an electronic device detects that a first file and a second file are duplicate files, with a first index node of the first file pointing to file data of the first file, and a second index node of the second file pointing to file data of the second file. The electronic device generates a target index node and configures the target index node to point to the file data of the first file. The electronic device associates the first index node with the target index node, and separately associates the second index node with the target index node. The electronic device then deletes the file data of the second file.Type: ApplicationFiled: December 8, 2024Publication date: March 27, 2025Applicant: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Jie Qiu, Wei Fang, Xie Miao, Jing Qian
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Publication number: 20250022437Abstract: Vehicles and related systems and adaptive display adjustment methods are provided. One method involves obtaining image data captured using an initial frame rate from an imaging system onboard the vehicle, obtaining current vehicle state information, determining a representative exposure setting for the imaging system based at least in part on the current vehicle state information, determining an estimated illuminance of a surrounding environment of the vehicle based at least in part on the image data and the representative exposure setting and automatically configuring the imaging system for a different, updated frame rate based on the estimated illuminance.Type: ApplicationFiled: July 13, 2023Publication date: January 16, 2025Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLCInventors: Mohamed A. Naiel, Daniel Xie, Yun Qian Miao, Sai Vishnu Aluru, Joseph G. Machak
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Patent number: 12130735Abstract: Data writing methods and computing devices are provided. An example data writing method is applied to a computer system, and the computer system includes a file system and a flash memory-based storage system. The example data writing method includes obtaining a target logical address, where the target logical address is an address allocated from a first logical block to target data to be written into the flash memory-based storage system, the first logical block is one of multiple logical blocks in the file system, and the flash memory-based storage system includes multiple physical blocks. It is determined that the target logical address belongs to the first logical block. The target data is written into a first physical block based on a correspondence between the first logical block and the first physical block, where the first physical block is one of the multiple physical blocks.Type: GrantFiled: December 28, 2022Date of Patent: October 29, 2024Assignee: Huawei Technologies Co., Ltd.Inventors: Wei Fang, Xie Miao, Tao Hou
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Patent number: 12050896Abstract: This application provides a system architecture switching method and apparatus. The method includes: when a system architecture needs to be switched, transforming a first system architecture into a second system architecture, where the first system architecture represents a system architecture before switching; and providing a service for a user by using the second system architecture. Dynamic switching of a system architecture is implemented by using a transformable system architecture, so that switching of different architectures can be implemented by using only one system architecture. Therefore, only code for implementing the system architecture is required, and code overheads can be reduced in comparison with a conventional technology.Type: GrantFiled: January 13, 2023Date of Patent: July 30, 2024Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Yuming Wu, Fangzhou Lu, Xie Miao
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Publication number: 20240192877Abstract: This application discloses a super block management method and apparatus. An example method includes: obtaining a parameter of a memory and a type of target data, where the target data is data to be written into the memory; configuring a capacity of a section in a file system based on at least one of the type of the target data or the parameter of the memory, where the configured capacity of the section matches a capacity of a super block in the memory; and managing, based on the configured capacity of the section, a logical address space corresponding to the memory.Type: ApplicationFiled: February 22, 2024Publication date: June 13, 2024Inventors: Laibin QIU, Wei FANG, Xie MIAO, Hongjiang ZHAO, Jie QIU
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Patent number: 11928359Abstract: A memory swapping method and apparatus are provided. The method includes: selecting n to-be-swapped-out pages; compressing the n to-be-swapped-out pages into n compressed blocks, and buffering the n compressed blocks in a compressed data buffer area; organizing at least one of the n compressed blocks into m to-be-written units; and writing the m to-be-written units into a swap area of a non-volatile storage device in a maximum of m batches, where at least one of the m to-be-written units is stored in a segment of continuous space in the swap area. The method reduces a quantity of write times during memory swapping, thereby prolonging a service life of the non-volatile storage device.Type: GrantFiled: July 19, 2022Date of Patent: March 12, 2024Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Chengke Wang, Yongjun Wei, Xie Miao, Wei Fang
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Publication number: 20230153236Abstract: Data writing methods and computing devices are provided. An example data writing method is applied to a computer system, and the computer system includes a file system and a flash memory-based storage system. The example data writing method includes obtaining a target logical address, where the target logical address is an address allocated from a first logical block to target data to be written into the flash memory-based storage system, the first logical block is one of multiple logical blocks in the file system, and the flash memory-based storage system includes multiple physical blocks. It is determined that the target logical address belongs to the first logical block. The target data is written into a first physical block based on a correspondence between the first logical block and the first physical block, where the first physical block is one of the multiple physical blocks.Type: ApplicationFiled: December 28, 2022Publication date: May 18, 2023Inventors: Wei FANG, Xie MIAO, Tao HOU
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Publication number: 20230153088Abstract: This application provides a system architecture switching method and apparatus. The method includes: when a system architecture needs to be switched, transforming a first system architecture into a second system architecture, where the first system architecture represents a system architecture before switching; and providing a service for a user by using the second system architecture. Dynamic switching of a system architecture is implemented by using a transformable system architecture, so that switching of different architectures can be implemented by using only one system architecture. Therefore, only code for implementing the system architecture is required, and code overheads can be reduced in comparison with a conventional technology.Type: ApplicationFiled: January 13, 2023Publication date: May 18, 2023Inventors: Yuming WU, Fangzhou LU, Xie MIAO
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Publication number: 20220350531Abstract: A memory swapping method and apparatus are provided. The method includes: selecting n to-be-swapped-out pages; compressing the n to-be-swapped-out pages into n compressed blocks, and buffering the n compressed blocks in a compressed data buffer area; organizing at least one of the n compressed blocks into m to-be-written units; and writing the m to-be-written units into a swap area of a non-volatile storage device in a maximum of m batches, where at least one to-be-written unit is stored in a segment of continuous space in the swap area. The method reduces a quantity of write times during memory swapping, thereby prolonging a service life of the non-volatile storage device.Type: ApplicationFiled: July 19, 2022Publication date: November 3, 2022Inventors: Chengke WANG, Yongjun WEI, Xie MIAO, Wei FANG
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Publication number: 20220253252Abstract: A data processing method and apparatus are provided. The data processing method is: receiving a write request, where the write request is for requesting to write, to an external memory, first data in a first storage area in an internal memory; writing the first data to a second storage area in the internal memory, where the second storage area is a storage area, in the internal memory, that is reallocated to the first data, and the second storage area is different from the first storage area; sending a response message after the first data is written to the second storage area, where the response message indicates that processing of the write request is completed; and writing the first data in the second storage area to the external memory.Type: ApplicationFiled: April 29, 2022Publication date: August 11, 2022Inventors: Wei FANG, Xie MIAO, Xiang GAO, Hongjiang ZHAO, Xu TANG
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Patent number: 10628216Abstract: An I/O request scheduling method includes storing received I/O requests into a plurality of queues, where each queue corresponds to at least one process group, each process group includes one or more processes, and a received I/O request is stored into a queue corresponding to a process group to which a process corresponding to the I/O request belongs, and dispatching the I/O requests in the plurality of queues to an I/O device, where a quantity of I/O requests from a high-priority queue is greater than a quantity of I/O requests from a low-priority queue during one dispatching procedure.Type: GrantFiled: May 2, 2019Date of Patent: April 21, 2020Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Xie Miao, Jiang Zhong, Kaixu Xia
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Publication number: 20190258514Abstract: An I/O request scheduling method includes storing received I/O requests into a plurality of queues, where each queue corresponds to at least one process group, each process group includes one or more processes, and a received I/O request is stored into a queue corresponding to a process group to which a process corresponding to the I/O request belongs, and dispatching the I/O requests in the plurality of queues to an I/O device, where a quantity of I/O requests from a high-priority queue is greater than a quantity of I/O requests from a low-priority queue during one dispatching procedure.Type: ApplicationFiled: May 2, 2019Publication date: August 22, 2019Inventors: Xie Miao, Jiang Zhong, Kaixu Xia
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Publication number: 20190258582Abstract: Embodiments of the present disclosure provide a DRAM-based storage caching method for a smart terminal, and the method includes: capturing an IO delivered by an upper-layer application; determining, based on a configuration policy, whether the IO belongs to a pre-specified to-be-cached IO type; and when the IO belongs to the pre-specified to-be-cached IO type, performing a corresponding caching operation for the IO in a DRAM disk based on a read/write type of the IO and a preset caching policy, where the DRAM disk is a block device created by using a reserved part of DRAM space of an operating system.Type: ApplicationFiled: May 1, 2019Publication date: August 22, 2019Inventors: Xie MIAO, Yijing WANG, Bintian WANG, Qiulin CHEN
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Publication number: 20180239726Abstract: The present invention provides a data transmission method, device, and system, to perform DMA data transmission between an I/O device and multiple host devices. DMA memory addresses of the multiple hosts are mapped, to virtual addresses in a global virtual address space, a DMA memory address and a target host that correspond to the DMA virtual address are determined according to a correspondence among DMA virtual addresses, DMA memory addresses, and hosts; the DMA virtual address in the DMA packet is modified to the DMA memory address mapped to the DMA virtual address; and the modified DMA packet is sent to the target host. DMA data transmission between an I/O device and multiple hosts can be implemented, utilization of the I/O device is improved, and application scenarios of network transmission are expanded.Type: ApplicationFiled: April 20, 2018Publication date: August 23, 2018Applicant: HUAWEI TECHNOLOGIES CO.,LTD.Inventors: Yijing Wang, Xie Miao