Abstract: Technology is disclosed related to methods and devices for reducing the top-level placement and routing runtime of a field-programmable gate arrays (FPGA). The method can comprise: generating a global signal netlist comprising feedthrough connections through non-adjacent FPGA modules; selecting a predefined signal connection pattern for the global signal netlist; generating pre-routed feedthrough connections based on the predefined signal connection pattern and the global signal netlist; and generating a pre-routed global signal netlist from the pre-routed feedthrough connections. The FPGA can comprise an FPGA module configured to send a pre-routed global signal to a non-adjacent FPGA module through a pre-routed feedthrough connection identified using a predefined signal connection pattern.

Abstract: Resistive random access memory (RRAM) based multiplexers and field programmable gate arrays (FPGAs) are provided. The RRAM-based multiplexers and FPGAs include a 4T1R programming structure to program the RRAMs. The programming structure includes two programming transistors connected between the power supply and the top electrode of the RRAM and two programming transistors connected between the power supply and the bottom electrode of the RRAM. The programming transistors are used to set and rest the RRAMs. In the RRAM-based multiplexer programming transistors connected to the bottom electrodes are shared between a plurality of RRAMs. The shared programming transistors and an output inverter of the RRAM are provided in a deep N-well of the RRAM-based multiplexer. The programming transistors connected to the top electrodes of the RRAMs and a plurality of input inverters are provided in a regular well of the RRAM-based multiplexer.

Abstract: Resistive random access memory (RRAM) based multiplexers and field programmable gate arrays (FPGAs) are provided. The RRAM-based multiplexers and FPGAs include a 4T1R programming structure to program the RRAMs. The programming structure includes two programming transistors connected between the power supply and the top electrode of the RRAM and two programming transistors connected between the power supply and the bottom electrode of the RRAM. The programming transistors are used to set and rest the RRAMs. In the RRAM-based multiplexer programming transistors connected to the bottom electrodes are shared between a plurality of RRAMs. The shared programming transistors and an output inverter of the RRAM are provided in a deep N-well of the RRAM-based multiplexer. The programming transistors connected to the top electrodes of the RRAMs and a plurality of input inverters are provided in a regular well of the RRAM-based multiplexer.

Abstract: A routing architecture for fast interconnections between Look-Up Tables (LUTs) in a group of Basic Logic Elements (BLEs), whereby a size of the group ranges from 1 to k+1, where k is the number of inputs of a LUT, and LUTs in the group are indexed from 1 to k+1, and whereby (a) an output of a LUTi, 1?i?k, connects to one of the inputs of routing multiplexers of LUTj, i<j?k+1, hence creating a fast interconnection between LUTs, each routing multiplexer of LUTm, 2?m?k+1, has only one input that is connected to the output of an other LUT, the output of LUT(k+1) being devoid of any connection to any one of the inputs of the routing multiplexers; (b) a subset of the inputs of LUT1 are connected to the outputs of other LUTs by means of fast interconnections, leaving the remaining inputs of LUT1 free of any fast interconnection, whereby for LUTp, 2?p?k+1, p?1 inputs of the LUTp are connected to the outputs of LUTq, 1?q?j, by means of fast interconnections; and (c) a cluster-based logic block contains at least one

Abstract: A routing architecture for fast interconnections between Look-Up Tables (LUTs) in a group of Basic Logic Elements (BLEs), whereby a size of the group ranges from 1 to k+1, where k is the number of inputs of a LUT, and LUTs in the group are indexed from 1 to k+1, and whereby (a) an output of a LUTi, 1?i?k, connects to one of the inputs of routing multiplexers of LUTj, i<j?k+1, hence creating a fast interconnection between LUTs, each routing multiplexer of LUTm, 2?m?k+1, has only one input that is connected to the output of an other LUT, the output of LUT(k+1) being devoid of any connection to any one of the inputs of the routing multiplexers; (b) a subset of the inputs of LUT1 are connected to the outputs of other LUTs by means of fast interconnections, leaving the remaining inputs of LUT1 free of any fast interconnection, whereby for LUTp, 2?p?k+1, p?1 inputs of the LUTp are connected to the outputs of LUTq, 1?q?j, by means of fast interconnections; and (c) a cluster-based logic block contains at least one

Abstract: A Field Programmable Gate Array (FPGA) of the island-type comprising a plurality of cluster-based Configurable Logic Blocks (CLBs), whereby each of the cluster-based CLBs is surrounded by a global routing structure formed by a plurality of multiplexers and pass/transmission-gates organized in Switch Boxes (SBs) and Connection Blocks (CBs), the switch boxes and the connection blocks comprising at least a first plurality of resistive memories inserted in a data path of a first routing architecture of the switch boxes and the connection blocks. Each CLB contains Basic Logic Elements (BLEs), as well as local routing resources.

Abstract: A Field Programmable Gate Array (FPGA) of the island-type comprising a plurality of cluster-based Configurable Logic Blocks (CLBs), whereby each of the cluster-based CLBs is surrounded by a global routing structure formed by a plurality of multiplexers and pass/transmission-gates organized in Switch Boxes (SBs) and Connection Blocks (CBs), the switch boxes and the connection blocks comprising at least a first plurality of resistive memories inserted in a data path of a first routing architecture of the switch boxes and the connection blocks. Each CLB contains Basic Logic Elements (BLEs), as well as local routing resources.