Abstract: A method and device for testing a memory are provided. The method includes the following operations. After activating at least one word line, at least two times of read operations are performed on a to-be-tested memory cell connected to the activated word line. Whether there is a read abnormality in the to-be-tested memory cell is determined according to an output signal obtained after the at least two times of read operations.

Abstract: Provided are a sense amplifying circuit and method, and a semiconductor memory. The sense amplifying circuit includes: a transmission circuit, configured to receive a signal to be processed and perform transmission on the signal to be processed to obtain an initial transmission signal; and an amplifying circuit, configured to receive a first control signal and the signal to be processed, and perform amplification on the initial transmission signal according to the first control signal and the signal to be processed to obtain a target transmission signal.

Abstract: A method and device for testing a memory and a method for simulated testing include operations as follows. First data is written into a to-be-tested storage unit through a Sense Amplifier (SA), second data different from the first data is written into the storage unit through the SA, and an amplification duration of the SA is shortened during the writing the second data, and data stored in the storage unit is read, and whether the storage unit is abnormal is determined according to the read data.

Abstract: A method for determining a sense boundary of a sense amplifier includes: writing the same data into the memory cells controlled by at least a pair of first word line on the left side and second word line on the right side corresponding to the sense amplifier; activating the first word line and precharging bit lines corresponding to the first word line; reading the data in the memory cells controlled by the corresponding second word line after a preset row precharge time; and determining a corresponding critical row precharge time as a row precharge time boundary value when the sense amplifier does not correctly read the data in the memory cells controlled by the second word line.

Abstract: Embodiments provide a method for sense margin detection for a sense amplifier and an electronic device. The method includes: writing first data and second data respectively to a first memory cell and a second memory cell connected to a first bit line, the first memory cell and the second memory cell being respectively connected to a first word line and a second word line adjacent to each other, and the first bit line being connected to a first sense amplifier; performing a reverse write operation on the first memory cell and the second memory cell; performing write operations on memory cells connected to the second bit line; and reading the second memory cell, and determining the preset row precharge time to be a margin value of row precharge time of the first sense amplifier when the first data is not correctly read.

Abstract: Provided are a memory detection method, a computer device and a storage medium. The method includes: initializing all storage units in a storage unit array; determining a plurality of target wordlines, two adjacent target wordlines being provided with a plurality of interfering wordlines therebetween; turning on the target wordlines, and performing a write operation on storage units connected to the target wordlines; performing repeatedly turn-on and turn-off of the interfering wordlines for a plurality of times; and performing a read operation on the storage units connected to the target wordlines. A write operation is performed on the storage units connected to the interfering wordlines by means of forced current sinking.

Abstract: Provided are a method for testing a memory, an apparatus for testing a memory, a computer-readable storage medium, and an electronic device, which relate to the field of integrated circuit technology. The method for testing a memory includes: writing first data into each of memory cells of a memory array; enabling a data mask mode, and writing second data into each of the memory cells of the memory array; enabling a leakage mode, and writing the first data into a memory cell corresponding to a column under test of the memory array; and after preset leakage time, disabling the leakage mode, and reading data from the memory cell corresponding to the column under test for testing, to determine whether there are at least two columns simultaneously turned on in the memory array. This method may test whether a row decoder fails.

Abstract: The present application relates to the field of semiconductors, in particular, to the field of Dynamic Random Access Memories (DRAMs), and provides a method and system for detecting a mismatch of a sense amplifier. The method creates a sense amplifier by delaying switch-on of a positive channel-metal-oxide-semiconductor (PMOS) transistor or a negative channel-metal-oxide-semiconductor (NMOS) transistor in the sense amplifier and shortening a row precharge command period (tRP).

Abstract: Embodiments provide a method for sense margin detection for a sense amplifier and an electronic device. The method includes: writing first data and second data respectively to a first memory cell and a second memory cell connected to a first bit line, the first memory cell and the second memory cell being respectively connected to a first word line and a second word line adjacent to each other, and the first bit line being connected to a first sense amplifier; performing a reverse write operation on the first memory cell and the second memory cell; performing write operations on memory cells connected to the second bit line; and reading the second memory cell, and determining the preset row precharge time to be a margin value of row precharge time of the first sense amplifier when the first data is not correctly read.

Abstract: A method for determining a sense boundary of a sense amplifier includes: writing first data into a memory array; reading the first data in a first memory cell of the memory array, and reversely writing second data into the first memory cell; reading, after a preset row precharge time, the first data in a second memory cell on a bit line where the first memory cell is located; and reversely writing the second data into the second memory cell when the first data is read in the second memory cell.

Abstract: Provided are a method for testing a memory, an apparatus for testing a memory, a computer-readable storage medium, and an electronic device, which relate to the field of integrated circuit technology. The method for testing a memory includes: writing first data into each of memory cells of a memory array; enabling a data mask mode, and writing second data into each of the memory cells of the memory array; enabling a leakage mode, and writing the first data into a memory cell corresponding to a column under test of the memory array; and after preset leakage time, disabling the leakage mode, and reading data from the memory cell corresponding to the column under test for testing, to determine whether there are at least two columns simultaneously turned on in the memory array. This method may test whether a row decoder fails.

Abstract: A method for determining a sense boundary of a sense amplifier includes: writing the same data into at least a pair of first word line and second word line corresponding to both sides of the sense amplifier; activating and precharging the first word line; reading the data in the corresponding second word line after a preset row precharge time; and determining a corresponding critical row precharge time as a row precharge time boundary value when the sense amplifier does not correctly read the data in the second word line.

Abstract: A method for determining a sense boundary of a sense amplifier includes: writing first data into a memory array; reading the first data in a first memory cell of the memory array, and reversely writing second data into the first memory cell; reading, after a preset row precharge time, the first data in a second memory cell on a bit line where the first memory cell is located; and reversely writing the second data into the second memory cell when the first data is read in the second memory cell.

Abstract: Provided are a sense amplifying circuit and method, and a semiconductor memory. The sense amplifying circuit includes: a transmission circuit, configured to receive a signal to be processed and perform transmission on the signal to be processed to obtain an initial transmission signal; and an amplifying circuit, configured to receive a first control signal and the signal to be processed, and perform amplification on the initial transmission signal according to the first control signal and the signal to be processed to obtain a target transmission signal.

Abstract: A method and device for testing a memory and a method for simulated testing include operations as follows. First data is written into a to-be-tested storage unit through a Sense Amplifier (SA), second data different from the first data is written into the storage unit through the SA, and an amplification duration of the SA is shortened during the writing the second data, and data stored in the storage unit is read, and whether the storage unit is abnormal is determined according to the read data.

Abstract: Provided are a memory detection method, a computer device and a storage medium. The method includes: initializing all storage units in a storage unit array; determining a plurality of target wordlines, two adjacent target wordlines being provided with a plurality of interfering wordlines therebetween; turning on the target wordlines, and performing a write operation on storage units connected to the target wordlines; performing repeatedly turn-on and turn-off of the interfering wordlines for a plurality of times; and performing a read operation on the storage units connected to the target wordlines. A write operation is performed on the storage units connected to the interfering wordlines by means of forced current sinking.

Abstract: A method and device for testing a memory are provided. The method includes the following operations. After activating at least one word line, at least two times of read operations are performed on a to-be-tested memory cell connected to the activated word line. Whether there is a read abnormality in the to-be-tested memory cell is determined according to an output signal obtained after the at least two times of read operations.

Abstract: The present application relates to the field of semiconductors, in particular, to the field of Dynamic Random Access Memories (DRAMs), and provides a method and system for detecting a mismatch of a sense amplifier. The method creates a sense amplifier by delaying switch-on of a positive channel-metal-oxide-semiconductor (PMOS) transistor or a negative channel-metal-oxide-semiconductor (NMOS) transistor in the sense amplifier and shortening a row precharge command period (tRP).