Abstract: A phase interpolation circuit with a high linearity includes a first parallel circuit constituted by M phase interpolation units, and a second parallel circuit constituted by N phase interpolation units. An input terminal of the first parallel circuit is connected to a first clock input terminal and grounded via a first capacitor. An input terminal of the second parallel circuit is connected to a second clock input terminal and grounded via a second capacitor. An output terminal of the first parallel circuit and an output terminal of the second parallel circuit are connected to a clock output terminal and grounded via a zeroth capacitor. A circuit parameter of each phase interpolation unit corresponds to a target output weight respectively. The target output weight of each phase interpolation unit is determined by iteration to minimize a phase difference between all output clock signals of the phase interpolation circuit.

Abstract: A phase interpolation circuit with a high linearity includes a first parallel circuit constituted by M phase interpolation units, and a second parallel circuit constituted by N phase interpolation units. An input terminal of the first parallel circuit is connected to a first clock input terminal and grounded via a first capacitor. An input terminal of the second parallel circuit is connected to a second clock input terminal and grounded via a second capacitor. An output terminal of the first parallel circuit and an output terminal of the second parallel circuit are connected to a clock output terminal and grounded via a zeroth capacitor. A circuit parameter of each phase interpolation unit corresponds to a target output weight respectively. The target output weight of each phase interpolation unit is determined by iteration to minimize a phase difference between all output clock signals of the phase interpolation circuit.