Patents by Inventor Xilin Judy An

Xilin Judy An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SOI device with structure for enhancing carrier recombination and method of fabricating same
    Patent number: 7122863
    Abstract: A semiconductor-on-insulator (SOI) device. The SOI device includes an SOI wafer including an active layer, a substrate and a buried insulation layer disposed therebetween. The buried insulation layer includes an oxide trap region disposed along an upper surface of the buried insulation layer, the oxide trap region having a plurality of oxide traps to promote carrier recombination.
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: October 17, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dong-Hyuk Ju, William G. En, Srinath Krishnan, Xilin Judy An
  • SOI device with structure for enhancing carrier recombination and method of fabricating same
    Patent number: 6512244
    Abstract: A semiconductor-on-insulator (SOI) device. The SOI device includes an SOI wafer including an active layer, a substrate and a buried insulation layer disposed therebetween. The active layer includes an abrupt region disposed along a lower portion of the active layer, the abrupt region having the same P or N doping type as a doping type of a body region.
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: January 28, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dong-Hyuk Ju, William G. En, Srinath Krishnan, Xilin Judy An
  • Silicon-on-insulator transistors with asymmetric source/drain junctions formed by angled germanium implantation
    Patent number: 6479868
    Abstract: A silicon-on-insulator (SOI) transistor. The SOI transistor includes a germanium implanted source and drain having a body disposed therebetween, and a gate disposed on the body, the germanium being implanted at an angle such that the source has a concentration of germanium at a source/body junction and the gate shields germanium implantation in the drain adjacent a drain/body junction resulting in a graduated drain/body junction. Also disclosed is a method of fabricating the SOI transistor.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: November 12, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Xilin Judy An, Bin Yu, Concetta E. Riccobene