Abstract: A semiconductor package includes an interposer and a plurality of integrated circuit (IC) dice disposed on and intercoupled via the interposer. A first IC die has a clock speed rating that is greater than a clock speed rating of another of the IC dice. A plurality of programmable voltage tuners are coupled to the plurality of IC dice, respectively. A first voltage tuner is coupled to the first IC die, and the first voltage tuner is programmed to reduce a voltage level of voltage input to the first voltage tuner and output the reduced voltage to the first IC die.

Abstract: A circuit for implementing a gain stage in an integrated circuit is described. The circuit comprises a first inductor formed in a first plurality of metal layers; a second inductor formed in a second plurality of metal layers, the second inductor coupled to a center tap of the first inductor; and wherein the second inductor has a diameter that is less than a diameter of the first inductor. A method of implementing a gain stage in an integrated circuit is also described.

Abstract: An apparatus for calibration of a signal converter is disclosed. This apparatus includes a first digital-to-analog converter (“DAC”) and a calibration system coupled to an output port of the first DAC. The calibration system includes a second DAC. The calibration system is configured to provide an adjustment signal responsive to a spurious spectral performance parameter in an output of the first DAC. The spurious spectral performance parameter is sensitive to a timing error associated with the first DAC. The calibration system is coupled to provide the adjustment signal to the first DAC to correct the timing error of the first DAC.

Abstract: An apparatus relating generally to a system-on-chip is disclosed. In this apparatus, the system-on-chip has at least one analog block, an input/output interface, a data test block, and a processing unit. The processing unit is coupled to the input/output interface to control access to the at least one analog block. The data test block is coupled to the at least one analog block through the input/output interface. The processing unit is coupled to the data test block and configured to execute test code having at least one test pattern. The data test block under control of the test code executed by the processing unit is configured to test the at least one analog block with the test pattern.

Abstract: Devices and methods for performing a cyclic redundancy check are disclosed. For example, a device has a splitter for splitting a data word into a plurality of paths. The device also has a plurality of cyclic redundancy check units. Each of the units is for processing a respective one of the paths. In addition, each of the units includes a first output port for outputting a cyclic redundancy check value for a packet ending within the unit and a second output port for outputting a cyclic redundancy check value for a packet starting or ongoing within the unit.

Abstract: A method includes initiating a boot of a system-on-chip coupled to a boot device. The boot is initiated from boot code stored in nonvolatile memory responsive to a power-on-reset. Under control of the boot code: a first register value is loaded into a register; a name string from the boot code is accessed; the first register value is obtained from the register; and the first register value and name string are converted to a first string value, which is provided as a first filename. The boot device is searched for a boot image file with the first filename. If the first filename is not found in the boot device, the first register value is incremented to provide a second register value. The obtaining, converting, and searching are repeated using a second filename generated using the second register value, and a valid filename for the boot image file is iteratively generated.

Abstract: A method, non-transitory computer readable medium and apparatus for correcting a timestamp in a multi-lane communication link with a skew are disclosed. For example, the method receives a data packet, a time stamp for the data packet and a fill level for a lane of the multi-lane communication link carrying the data packet, calculates a corrected timestamp for the data packet and replaces the time stamp for the data packet with the corrected timestamp.

Abstract: A multi-layer core organic package substrate includes: a multi-layer core comprising at least two organic core layers, wherein two of the at least two organic core layers are separated by a core metal layer; a first plurality of build-up layers formed on top of the multi-core layer; and a second plurality of build-up layers formed below the multi-core layer.

Abstract: A substrate-less interposer for a stacked silicon interconnect technology (SSIT) product, includes: a plurality of metallization layers, at least a bottom most layer of the metallization layers comprising a plurality of metal segments, wherein each of the plurality of metal segments is formed between a top surface and a bottom surface of the bottom most layer of the metallization layers, and the metal segments are separated by dielectric material in the bottom most layer; and a dielectric layer formed on the bottom surface of the bottom most layer, wherein the dielectric layer includes one or more openings for providing contact to the plurality of metal segments in the bottom most layer.

Abstract: An integrated circuit device having memory is disclosed. The integrated circuit device comprises programmable resources; programmable interconnect elements coupled to the programmable resources, the programmable interconnect elements enabling a communication of signals with the programmable resources; a plurality of memory blocks; and dedicated interconnect elements coupled to the plurality of memory blocks, the dedicated interconnect elements enabling access to the plurality of memory blocks. A method of implementing memory in an integrated circuit device is also disclosed.

Abstract: An apparatus with package integrity monitoring capability, includes: a package having a die connected to an interposer through a plurality of bumps, wherein at least some of the bumps comprise dummy bumps; a package integrity monitor having a transmitter to transmit a test signal and a receiver to receive the test signal; and a first scan chain comprising a plurality of alternating interconnects in the die and in the interposer connecting some of the dummy bumps in series, wherein the first scan chain has a first end coupled to the transmitter of the package integrity monitor and a second end coupled to the receiver of the package integrity monitor.

Abstract: A reticle for multiple patterning a layer of an integrated circuit die includes a first portion with a first layout pattern for multiple patterning the layer of the integrated circuit die, and a second portion with a second layout pattern for multiple patterning the layer of the integrated circuit die. The first layout pattern is different from the second layout pattern.

Abstract: A circuit for enabling the discharge of electric charge in an integrated circuit is described. The circuit comprises an input/output pad coupled to a first node; a first diode coupled between the first node and a ground node; a transistor coupled in parallel with the first diode between the first node and ground node; and a resistor coupled between a body portion of the transistor and the ground node. A method of enabling the discharge of electric charge is also described.

Abstract: A method performed by an information handling system for on-the-fly technical support is described. In an exemplary method, an error message is read to obtain an error code therefrom. A project directory is searched to obtain a report; where the report indicates a failed module of a plurality of executable modules, and where the report is associated with the error message. A source of an error is identified from the error message. A failed stage of the failed module is identified from the report. A case inquiry for the error message is prepared for searching a document for resolution of the error, where the case inquiry identifies the failed stage. A network is accessed, and the case inquiry is sent over the network.

Abstract: An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; a P-well formed on the substrate and having N-type transistors of a memory cell; and an N-well formed on the substrate and having P-type transistors of the memory cell; wherein the N-well has minimal dimensions for accommodating the P-type transistors.

Abstract: An apparatus includes an integrated circuit with a clock network in an array of circuit blocks. The clock network includes routing tracks, distribution spines, and clock leaves. The routing tracks and the distribution spines are bidirectional.

Abstract: A circuit includes a first input terminal, a first transmission line, a first sampling switch coupled to the first input terminal through the first transmission line, a first sampling capacitor coupled to the sampling switch, and a first open-circuit quarter wavelength stub coupled to the first transmission line, the first open-circuit quarter wavelength stub configured to reduce kickback noise on the first transmission line. A method for reducing kickback noise in a circuit includes determining a frequency associated with a kickback noise on a first transmission line of the circuit, the circuit having an input terminal coupled to the first transmission line, configuring a length of an open-circuit quarter wavelength stub to correspond to the determined frequency, and coupling the open-circuit quarter wavelength stub to the first transmission line to filter the frequency associated with the kickback noise.

Abstract: A method of performing digital pre-distortion in a communication network is described. The method comprises implementing a transceiver in the communication network, the transceiver enabling the transfer of communication signals in the communication network by way of a wireless communication channel; sampling signals, at the transceiver, associated with a transmit signal which are necessary to perform digital pre-distortion; providing the sampled signals to a remote computer; and generating, at the remote computer, parameters to be applied to a digital pre-distortion circuit of the transceiver. A communication network configured to enable digital pre-distortion is also described.

Abstract: An embodiment of a memory module is disclosed. This memory module is a configurable hard macro. A portion of this memory module includes a data input multiplexer coupled to select between cascaded data and direct/bused data. Such portion further includes, a memory coupled to receive output from the data input multiplexer for storage therein, and a register input multiplexer coupled to select between read data from the memory and the cascaded data. This memory module further includes: a register coupled to receive output from the register input multiplexer, a latch/register mode multiplexer coupled to select between the read data from the memory and registered data from the register, and a data output multiplexer coupled to select between the cascaded data and output from the latch/register mode multiplexer to provide output data.

Abstract: An inductor structure implemented within a semiconductor integrated circuit includes a coil of conductive material including at least one turn and a current return encompassing the coil. The current return is formed of a plurality of interconnected metal layers of the semiconductor integrated circuit.