Abstract: The state of an interrupt is identified. An eligibility value corresponding to the interrupt is generated based on the state of the interrupt. The eligibility value is indicative of whether the interrupt should be processed by a first processing path or a second processing path, the second processing path being lower latency than the first processing path, and the second processing path bypassing operations performed in the first processing path. When an interrupt is received at an assembly language processing system, from a hardware device, the assembly language processing system accesses the eligibility value corresponding to the interrupt and routes the interrupt to the first or second processing path based on the eligibility value.

Abstract: A method for multiplexing access of the performance monitoring hardware in different modes includes providing a first mode at one or more guest partitions and providing a second mode at a management partition. Each of one or more guest partitions and the management partition is a virtual machine managed by a hypervisor. The first mode enables a guest partition access to the performance monitoring hardware for a corresponding partition. The second mode enables a management partition access to the performance monitoring hardware for at least one guest partition. The first mode has a first priority, and the second mode has a second priority that is lower than the first priority, such that when the first mode at a particular guest partition is enabled, the corresponding second mode at the management partition is automatically disabled.

Abstract: Method, systems, and computer program products for managing a processor power management feature on behalf of a virtual machine (VM). A device may determine that a VM operating at a computer system possesses a power management entitlement. The device may identify an architectural power management feature available at a physical processor core of a processor system. The physical processor core is associated with a virtual processor core of the VM. Based on the VM possessing the power management entitlement, the device may present an interface to the VM. The interface exposes the architectural power management feature to the VM. The device may identify a request from the VM to modify a state of the architectural power management feature. Based on the request, the device may modify the state of the architectural power management feature at the physical processor core.

Abstract: A computer system supports a nested isolation host. The computer system operates a hypervisor that creates a virtualized interface to a security module that is configured to provide hardware-based virtual machine isolation functionality, and that creates a child partition that comprises a nested hypervisor. The hypervisor presents the virtualized interface to the child partition. Based on receiving a command at the virtualized interface from the nested hypervisor, the hypervisor performs one of (i) modifying the command and forwarding a modified command to the security module, (ii) forwarding the command to the security module, or (iii) blocking the command.

Abstract: Hierarchical virtualization creates a child guest partition that shares a hypervisor with a parent guest partition. A hypervisor receives a request, from a first guest partition that operates at the hypervisor, to create a second guest partition as a child of the first guest partition. The hypervisor identifies a configuration specification for the second guest partition, which includes (1) an identification of a memory portion, which is allocated to the first guest partition, that is to be mapped into the second guest partition; and (2) a configuration of a virtual processor that is to be utilized by the second guest partition. The hypervisor creates the second guest partition based on the configuration specification.

Abstract: Isolating resources of a virtual machine (VM) guest from a host operating system. A computer system receives an acceptance request from a guest partition corresponding to an isolated VM. The acceptance request identifies a guest memory page that is mapped into a guest physical address space of the guest partition, and a memory page visibility class. The computer system determines whether a physical memory page that is mapped to the guest memory page meets the memory page visibility class. The computer system sets a page acceptance indication for the guest memory page from an unaccepted state to an accepted state based on the physical memory page meeting the memory page visibility class.

Abstract: This disclosure generally relates to enabling a hypervisor of a host machine to provide virtual interrupts to select virtual processors or a set of virtual processors. More specifically, the present disclosure describes how interrupts may be provided to targeted virtual processors, regardless of where the virtual processors are currently executing. That is, when an interrupt is received, the interrupt may be delivered to a specified virtual processor regardless of which logical processor is currently hosting the virtual processor.

Abstract: This disclosure generally relates to enabling a hypervisor of a host machine to provide virtual interrupts to select virtual processors or a set of virtual processors. More specifically, the present disclosure describes how a hypervisor of a host machine may monitor the status of one or more virtual processors that are executing on the host machine and deliver interrupts to the virtual processors based on a number of factors including, but not limited to, a priority of the interrupt, a priority of the virtual processor, a current workload of the virtual processor and so on.

Abstract: This disclosure generally relates to enabling a hypervisor of a host machine to provide virtual interrupts to select virtual processors or a set of virtual processors. More specifically, the present disclosure describes how a hypervisor of a host machine may monitor the status of one or more virtual processors that are executing on the host machine and deliver interrupts to the virtual processors based on a number of factors including, but not limited to, a priority of the interrupt, a priority of the virtual processor, a current workload of the virtual processor and so on.

Abstract: This disclosure generally relates to time and timer techniques that may be used to virtualize one or more virtual machines. In an example, it may be possible to save and restore a timer of a virtual machine while preserving timer information associated with the timer (e.g., an expiration time, whether the most recent expiration has been signaled, and the enable bit, etc.). For example, a first mode may enable restoring a timer based on a previously-existing enable bit, thereby retaining the state of the timer (e.g., whether the timer is programmed to fire and/or whether the most recent expiration has been signaled). By contrast, a second mode of setting a timer may automatically set the enable bit, thereby automatically enabling the timer to fire, as may be expected by a virtual machine when setting a timer.

Abstract: This disclosure generally relates to hypervisor memory virtualization. Techniques disclosed herein improve peripheral component interconnect express (PCI-e) device interoperability with a virtual machine. As an example, when a direct-memory access request is received from a PCI-e device but the target memory is currently unmapped, an indication may be provided to a memory paging processor so as to page-in the memory, such that the PCI-e device may continue to function normally. In some examples, the access request may be buffered and replayed once the memory is paged-in, or the access request may be retried, among other examples.

Abstract: Speculative side channels exist when memory is accessed by speculatively-executed processor instructions. Embodiments use uncacheable memory mappings to close speculative side channels that could allow an unprivileged execution context to access a privileged execution context's memory. Based on allocation of memory location(s) to the unprivileged execution context, embodiments map these memory location(s) as uncacheable within first page table(s) corresponding to the privileged execution context, but map those same memory locations as cacheable within second page table(s) corresponding to the unprivileged execution context. This prevents a processor from carrying out speculative execution of instruction(s) from the privileged execution context that access any of this memory allocated to the unprivileged execution context, due to the unprivileged execution context's memory being mapped as uncacheable for the privileged execution context.

Abstract: This disclosure generally relates to hypervisor memory virtualization. In an example, multiple page table stages may be used to provide a page table that may be used by a processor when processing a workload for a nested virtual machine. An intermediate (e.g., nested) hypervisor may request an additional page table stage from a parent hypervisor, which may be used to virtualize memory for one or more nested virtual machines managed by the intermediate hypervisor. Accordingly, a processor may use the additional page table stages to ultimately translate a virtual memory address for a nested virtual machine to a physical memory address.

Abstract: This disclosure generally relates to hypervisor memory virtualization. Techniques disclosed herein improve peripheral component interconnect express (PCI-e) device interoperability with a virtual machine. As an example, when a direct-memory access request is received from a PCI-e device but the target memory is currently unmapped, an indication may be provided to a memory paging processor so as to page-in the memory, such that the PCI-e device may continue to function normally. In some examples, the access request may be buffered and replayed once the memory is paged-in, or the access request may be retried, among other examples.

Abstract: Speculative side channels exist when memory is accessed by speculatively-executed processor instructions. Embodiments use uncacheable memory mappings to close speculative side channels that could allow an unprivileged execution context to access a privileged execution context's memory. Based on allocation of memory location(s) to the unprivileged execution context, embodiments map these memory location(s) as uncacheable within first page table(s) corresponding to the privileged execution context, but map those same memory locations as cacheable within second page table(s) corresponding to the unprivileged execution context. This prevents a processor from carrying out speculative execution of instruction(s) from the privileged execution context that access any of this memory allocated to the unprivileged execution context, due to the unprivileged execution context's memory being mapped as uncacheable for the privileged execution context.

Abstract: This disclosure generally relates to enabling a hypervisor of a host machine to provide virtual interrupts to select virtual processors or a set of virtual processors. More specifically, the present disclosure describes how interrupts may be provided to targeted virtual processors, regardless of where the virtual processors are currently executing. That is, when an interrupt is received, the interrupt may be delivered to a specified virtual processor regardless of which logical processor is currently hosting the virtual processor.

Abstract: This disclosure generally relates to enabling a hypervisor of a host machine to provide virtual interrupts to select virtual processors or a set of virtual processors. More specifically, the present disclosure describes how a hypervisor of a host machine may monitor the status of one or more virtual processors that are executing on the host machine and deliver interrupts to the virtual processors based on a number of factors including, but not limited to, a priority of the interrupt, a priority of the virtual processor, a current workload of the virtual processor and so on.

Abstract: This disclosure generally relates to hypervisor memory virtualization. In an example, translation lookaside buffer (TLB) invalidation requests may be selectively delivered to processors to which they relate or may be ignored by processors to which they do not relate, so as to minimize the processing overhead that may be ordinarily associated with such TLB invalidation requests. In another example, a TLB invalidation request may be suspended in order to enable a hypervisor to finish executing instructions relating to one or more TLB entries that would be affected by the TLB invalidation request.

Abstract: This disclosure generally relates to time and timer techniques that may be used to virtualize one or more virtual machines. In an example, a plurality of host machines may each have clocks that operate at pre-determined or known frequencies, such that it may be possible to easily migrate a virtual machine from one host machine to another host machine using an offset, thereby providing consistent time information to the virtual machine. In some examples, a scale factor or multiplier may also be used in order to achieve a consistent frequency. For example, a first host machine may have a clock operating at 1 GHz, while a second host machine may have a clock operating at 500 MHz. In such an example, a multiplier may be used to double the frequency of the second host machine to match the clock of the first host machine, thereby providing consistent time information.

Abstract: This disclosure generally relates to hypervisor memory virtualization. In an example, multiple page table stages may be used to provide a page table that may be used by a processor when processing a workload for a nested virtual machine. An intermediate (e.g., nested) hypervisor may request an additional page table stage from a parent hypervisor, which may be used to virtualize memory for one or more nested virtual machines managed by the intermediate hypervisor. Accordingly, a processor may use the additional page table stages to ultimately translate a virtual memory address for a nested virtual machine to a physical memory address.