Abstract: An IC structure includes first through third n-wells aligned along a first direction in a semiconductor substrate, wherein the first n-well is separated from each of the second and third n-wells by corresponding spaces, a first plurality of active areas, gate structures, and metal-like defined (MD) segments overlying and electrically connected to the active areas positioned in the first n-well, a first tap structure overlying and electrically connected to the second n-well, a second tap structure overlying and electrically connected to the third n-well, and a first metal segment extending in the first direction, overlying the first plurality of transistors, and electrically connected to each of the first and second tap structures.