Abstract: The present application relates to the field of communications, and provides a transmission method and apparatus. The method includes a network side device determines a number of Demodulation Reference Signal (DMRS) port groups N occupied by downlink transmission data sent to a terminal, N being greater than or equal to 1; the network side device determines, according to the number of the DMRS port groups occupied by the downlink transmission data, a code word transmission mode corresponding to the downlink transmission data; and the network side device performs data processing on the downlink transmission data according to the code word transmission mode, and transmits the processed downlink transmission data by means of transmission points corresponding to the N DMRS port groups.

Abstract: The present application can provide an uplink transmission method and apparatus. The method comprises: a base station instructs a UE to send SRSs corresponding to N groups of SRS resources, each of the N groups of SRS resources comprising one or more SRS resources; N being a positive integer; the base station receives the SRSs sent by the UE to determine X groups of uplink scheduling information, each of the X groups of uplink scheduling information corresponding to one group of SRS resources in the N groups of SRS resources; uplink scheduling information in different groups corresponding to SRS resources in different groups; X being a positive integer greater than one and not greater than N; the base station sends the determined X groups of uplink scheduling information to the UE so that the UE transmits an uplink signal according to the X groups of uplink scheduling information.

Abstract: Various structures that implement topside metal routing and backside metal routing in combination with vertical transistors are disclosed. The various structures include cells that form inverter devices, NAND devices, and MUX (multiplexer) devices. The disclosed cells include two or four vertical transistors with various connections made to the transistors that include either connected gate logic for inverter and NAND devices or disconnected gate logic for MUX devices.

Abstract: A SRAM cell layout that implements stacked transistors is disclosed. The cell layout utilizes both topside metal routing and backside metal routing along with stacked transistors to provide multiple transistors for implementation of inverters and pass gates in a memory cell. Various connection routes between components of the transistors (e.g., gates, sources, and drains) are made to allow cross-coupling between inverters in the memory cell.

Abstract: A cell layout that implements stacked transistors is disclosed. The cell layout utilizes both topside metal routing and backside metal routing. Various connection routes between components of the transistors (e.g., gates, sources, and drains) and either the topside metal routing or the backside metal routing can be made. The specific connection routes can be determined based on a desired device construction. Thus, the cell layout disclosed enables various devices to be constructed based on a basic cell structure.

Abstract: Various structures that implement topside metal routing and backside metal routing in combination with vertical transistors are disclosed. The various structures include a building block cell with a metal contact layer between the backside metal routing and the vertical transistors. Various connections can be made within the building block cell to form more complex structures such as, but not limited to, inverter devices, NAND devices, and MUX (multiplexer) devices.

Abstract: A memory device layout that implements SRAM cells with stacked transistors is disclosed. The memory utilizes both topside metal routing and backside metal routing for routing of bitlines between bit cells with stacked transistors and logic cells coupled to the bit cells.

Abstract: A bubble detection device and a sample processing instrument are provided. The bubble detection device includes a body, a cover and a detection circuit board. The body includes a bottom wall and first and second side walls respectively extending from two sides of the bottom wall. The bottom, first and second side walls define a groove for accommodating a sample pipe of a sample processing instrument, and first and second holes are respectively provided in the first and second side walls to allow light from a light source to pass through the sample pipe. The cover includes a top portion for covering the groove and first and second side portions attached to the body. The detection circuit board includes the light source and a photoelectric sensor and is attached to the body such that they are aligned with the first and second holes respectively to sense intensity of the light passing through the sample pipe. The sample processing instrument includes the bubble detection device.

Abstract: Provided herein, in certain embodiments, are various methods, reagents, and devices for detection of multiple target nucleic acids in a sample, or multiple segments of a target nucleic acid in a sample, using a programmable nuclease. In certain embodiments, the present disclosure provides compositions of pools of guide nucleic acids, programmable nucleases, and detector nucleic acids and methods of using said compositions for detection of different segments of one target nucleic acid or different target nucleic acids in a sample.

Abstract: A method and device for testing a positioning and speed measuring system main unit. The method includes: obtaining a first simulation signal by simulating an absolute position sensor and a relative position sensor; sending the first simulation signal to a main unit of a to-be-tested positioning and speed measuring system; obtaining a first result calculated by the main unit based on the first simulation signal; obtaining a second result calculated based on the first simulation signal, the second result being a reference result corresponding to the first simulation signal; and determining that the main unit is abnormal if a comparison between the first result and the second result exceeds a first preset range. Therefore, the main unit can still be tested without components including absolute position sensors and relative position sensors, the test process is simple and easy to implement, a test environment can be built without large-scale investment.

Abstract: Vertical transport field-effect transistors are formed on active regions wherein the active regions each include a wrap-around metal silicide contact on vertically extending side walls of the active region. Such wrap-around contacts form self-aligned and reliable strapping for SRAM bottom nFET and pFET source/drain regions. Buried contacts of SRAM cells may be used to strap the wrap-around metal silicide contacts with the gates of inverters thereof. Wrap-around metal silicide contacts provide additional contacts for logic FETs and reduce parasitic bottom source/drain resistance.

Abstract: A semiconductor structure includes a plurality of fins on a semiconductor substrate, the plurality of fins including an alternating sequence of a first nanosheet made of epitaxially grown silicon and a second nanosheet made of epitaxially grown silicon germanium, and a shallow trench isolation region within the semiconductor substrate adjacent to the plurality of fins. The shallow trench isolation region including a recess within the substrate filled with a first liner, a second liner directly above the first liner, a third liner directly above the second liner, and a dielectric material directly above the third liner. The first liner is made of a first oxide material, the third liner is made of a nitride material, and the second liner is made of a second oxide material that creates a dipole effect for neutralizing positive charges within the third liner and positive charges between the third liner and the first liner.

Abstract: A vertical field-effect transistor includes a substrate comprising a semiconductor material; a first set of fins formed from the semiconductor material and extending vertically with respect to the substrate; and a second set of fins extending vertically with respect to the substrate, wherein ones of the second set of fins abut ones of the first set of fins. The second set of fins comprises a dielectric material.

Abstract: Described herein are devices, systems, fluidic devices, kits, and methods for detection of target nucleic acids associated with diseases, cancers, genetic disorders, a genotype, a phenotype, or ancestral origin. The devices, systems, fluidic devices, kits, and methods may comprise reagents of a guide nucleic acid targeting a target nucleic acid, a programmable nuclease, and a single stranded detector nucleic acid with a detection moiety. The target nucleic acid of interest may be indicative of a disease, and the disease may be communicable diseases, or of a cancer or genetic disorder. The target nucleic acid of interest may be indicative of a genotype, a phenotype, or ancestral origin.

Abstract: A travelling-type tunnel hard-rock micro-damage cutting equipment and a construction method associated therewith are provided. The cutting equipment includes: a crawler-type trolley; and a hard-rock drilling construction apparatus, a hard-rock cutting construction apparatus, a self-unloading tipping bucket and a visual operation terminal all arranged on the crawler-type trolley. The hard-rock cutting construction apparatus includes: a cutting manipulation room, a rock-breaking power arm, and a hard-rock cutting device including a hydraulic steel robs, a signal sensor, an infrared lens and a light source assembly. The infrared lens and the light source assembly are arranged at the front end of the hard-rock cutting device, and a working image can be transmitted to the visual operation terminal through the signal sensor. The cutting equipment can accurately and efficiently cut a rock mass, and the cut rock mass can be reused according to secondary processing conditions of rock to improve economic benefits.

Abstract: A method for manufacturing a semiconductor device includes forming a source layer on a semiconductor substrate, forming a channel layer on the source layer, and forming a drain layer on the channel layer. The source, channel and drain layers are patterned into at least one fin, and a cap layer is formed on a lower portion of the at least one fin. The lower portion of the at least one fin includes the source layer and part of the channel layer. The method further includes forming a gate structure comprising a gate dielectric layer and a gate conductor on the at least one fin and on the cap layer. The cap layer is positioned between the lower portion of the at least one fin and the gate dielectric layer.

Abstract: Devices and methods are provided for forming single diffusion break isolation structures for integrated circuit devices including gate-all-around FET devices such as nanosheet FET devices and nanowire FET devices. For example, a semiconductor integrated circuit device includes first and second gate-all-around field-effect transistor devices disposed in first and second device regions, respectively, of a semiconductor substrate. A single diffusion break isolation structure is disposed between the first and second device regions. The single diffusion break isolation structure includes a dummy gate structure disposed on the semiconductor substrate between a first source/drain layer of the first gate-all-around field-effect transistor device and a second source/drain layer of the second gate all-around field-effect transistor device. The single diffusion break isolation structure is configured to electrically isolate the first and second source/drain layers.

Abstract: A method of fabricating a semiconductor device is described. The method includes forming a nanosheet stack on a substrate, the nanosheet stack includes nanosheet channel layers. A gate is formed around the nanosheet channel layers of the nanosheet stack. A strained material is formed along a sidewall surface of the gate. The strained material is configured to create strain in the nanosheet channel layers of the nanosheet stack.

Abstract: Methods and apparatuses are provided for movie and television series video data analysis. The method includes: gathering and reading, by a processor, a plurality of input movies; removing a video border of each input movie; splitting the input movie into short clips, based on accuracy and efficiency requirements of different analyzing models; assessing attributes of each input movie by analyzing, with the different analyzing models, the input movie, the short clips cut from the input movie, and the frame images extracted from the input movie; and summarizing the plurality of input movies based on matching and integrating the attributes assessed for each input movie.

Abstract: Methods and apparatuses are provided for movie and television series video data analysis. The method includes: gathering and reading, by a processor, a plurality of input movies; removing a video border of each input movie; splitting the input movie into short clips, based on accuracy and efficiency requirements of different analyzing models; assessing attributes of each input movie by analyzing, with the different analyzing models, the input movie, the short clips cut from the input movie, and the frame images extracted from the input movie; and summarizing the plurality of input movies based on matching and integrating the attributes assessed for each input movie.