Abstract: The present disclosure relates to a nucleic acid construct and use thereof. Specifically, the present disclosure relates to a nucleic acid construct comprising an engineered UTR, and use thereof in the prevention and treatment of a disease (for example, prevention of virus infection). The UTR can significantly improve the expression efficiency of a target gene in the nucleic acid construct.

Abstract: A preparation method for a large crystal region high crystallinity carbonaceous fiber, where a wet spinning method is mainly used to assemble graphene oxide and other polymer materials in liquid phase, a two-dimensional graphene oxide sheet performs a “template orienting effect” on polymer molecules, making the directional crystallization of polymer molecules, resulting in fiber with high orientation and crystallinity. Graphene sheet catalyzes pyrolyzed molecules through a “graphitization inducing effect” to directionally generate graphene-like carbon layers after following high temperature treatment, thereby promoting stacking behavior of graphene sheets, and a composite carbonaceous fiber with an optimal crystallinity is prepared. The graphene fiber material prepared by the present method has characteristics of low cost, high crystallinity and high performance, and can be applied to a field of lightweight structural materials.

Abstract: This disclosure is directed to methods, compounds and compositions for delivering nucleic acids to a cell of interest. In particular, it provides salts that are particularly effective in delivering nucleic acids to cells in the lung for disorders such as cystic fibrosis (CF).

Abstract: This disclosure is directed to methods, compounds and compositions for delivering nucleic acids to a cell of interest. In particular, it provides salts that are particularly effective in delivering nucleic acids to cells in the lung for disorders such as cystic fibrosis (CF).

Abstract: A segmented direct gate drive circuit of a depletion mode GaN power device, a gate voltage of the GaN power device is charged from a negative voltage turn-off level to a threshold voltage of the GaN power device; when the gate voltage of the GaN power device is charged to the threshold voltage of the GaN power device, a current mirror charging module first turns on less than N of charging current mirror modules to charge the gate voltage of the GaN power device from the threshold voltage of the GaN power device to a Miller platform voltage of the GaN power device, and turns on N charging current mirror modules to charge the gate voltage of the GaN power device from the Miller platform voltage of the GaN power device to a zero level.

Abstract: A switch bootstrap charging circuit suitable for a gate drive circuit of a GaN power device includes a high-voltage MOSFET, a low-voltage MOSFET, a high-voltage MOSFET control module, and a low-voltage MOSFET control module. The low-voltage MOSFET is a PMOS transistor, and the source of the low-voltage MOSFET is connected to the power supply voltage. The drain of the high-voltage MOSFET serves as an output terminal of the switch bootstrap charging circuit. The low-voltage MOSFET control module and the high-voltage MOSFET control module generate a gate drive signal of the low-voltage MOSFET and a gate drive signal of the high-voltage MOSFET according to the gate drive signal of the lower power transistor.

Abstract: A switch bootstrap charging circuit suitable for a gate drive circuit of a GaN power device includes a high-voltage MOSFET, a low-voltage MOSFET, a high-voltage MOSFET control module, and a low-voltage MOSFET control module. The low-voltage MOSFET is a PMOS transistor, and the source of the low-voltage MOSFET is connected to the power supply voltage. The drain of the high-voltage MOSFET serves as an output terminal of the switch bootstrap charging circuit. The low-voltage MOSFET control module and the high-voltage MOSFET control module generate a gate drive signal of the low-voltage MOSFET and a gate drive signal of the high-voltage MOSFET according to the gate drive signal of the lower power transistor.

Abstract: This disclosure is directed to methods, compounds and compositions for delivering nucleic acids to a cell of interest. In particular, it provides salts that are particularly effective in delivering nucleic acids to cells in the lung for disorders such as cystic fibrosis (CF).

Abstract: A ripple pre-amplification based fully integrated LDO pertains to the technical field of power management. The positive input terminal of a transconductance amplifier is connected to a reference voltage Vref, and the negative input terminal of the transconductance amplifier is connected to the feedback voltage Vfb. The output terminal of the transconductance amplifier is connected to the negative input terminal of a transimpedance amplifier and the negative input terminal of an error amplifier. The positive input terminal of the transimpedance amplifier is connected to the ground GND, and the output terminal of the transimpedance amplifier is connected to the positive input terminal of the error amplifier. The gate terminal of the power transistor MP is connected to the output terminal of the error amplifier, the source terminal of the power transistor MP is connected to an input voltage VIN, and the drain terminal of the power transistor MP is grounded.

Abstract: Methods of administering an oligonucleotide of interest into a cell in vitro or in vivo are described. In the methods, a small organic compound active agent is concurrently administered to the cell in an amount effective to increase the delivery of the oligonucleotide into the cell, and/or increase the activity of said oligonucleotide in the cell. Compositions useful for carrying out the method are also described.

Abstract: A ripple pre-amplification based fully integrated LDO pertains to the technical field of power management. The positive input terminal of a transconductance amplifier is connected to a reference voltage Vref, and the negative input terminal of the transconductance amplifier is connected to the feedback voltage Vfb. The output terminal of the transconductance amplifier is connected to the negative input terminal of a transimpedance amplifier and the negative input terminal of an error amplifier. The positive input terminal of the transimpedance amplifier is connected to the ground GND, and the output terminal of the transimpedance amplifier is connected to the positive input terminal of the error amplifier. The gate terminal of the power transistor MP is connected to the output terminal of the error amplifier, the source terminal of the power transistor MP is connected to an input voltage VIN, and the drain terminal of the power transistor MP is grounded.

Abstract: A low-dropout regulator with super transconductance structure relates to the field of power management technology. The super-transconductance structure refers to the circuit structure in which the voltage signal is converted into a current signal and amplified with a high magnification. The error amplifier EA in the present invention uses the super transconductance structure. The differential input pair of the error amplifier EA samples the difference between the feedback voltage VFB and the dynamic reference voltage VREF1. The difference is converted into a small signal current, which goes through a first-stage of current mirror to be amplified by K1, and through a second-stage of current mirror to be amplified by K2. The amplified signal is used to regulate the gate of the adjustment transistor MP. The error amplifier EA with the super transconductance structure is used to expand the bandwidth of the error amplifier EA.

Abstract: A low-dropout regulator with super transconductance structure relates to the field of power management technology. The super-transconductance structure refers to the circuit structure in which the voltage signal is converted into a current signal and amplified with a high magnification. The error amplifier EA in the present invention uses the super transconductance structure. The differential input pair of the error amplifier EA samples the difference between the feedback voltage VFB and the dynamic reference voltage VREF1. The difference is converted into a small signal current, which goes through a first-stage of current mirror to be amplified by K1, and through a second-stage of current mirror to be amplified by K2. The amplified signal is used to regulate the gate of the adjustment transistor MP. The error amplifier EA with the super transconductance structure is used to expand the bandwidth of the error amplifier EA.

Abstract: A low-dropout regulator, including: a dynamic pole tracking circuit having an active load, a voltage-to-current converter, a current amplifier, a bias circuit, a regulating transistor, a first feedback resistor, a second feedback resistor, and a first capacitor. The dynamic pole tracking circuit includes: a first PMOS, a second PMOS, a first resistor, and a second resistor. The voltage-to-current converter includes: a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, a fifth NMOS, a sixth NMOS, a seventh NMOS, an eighth NMOS, a third PMOS, a fourth PMOS, a seventh PMOS, an eighth PMOS. The current amplifier includes: a fifth PMOS, a sixth PMOS, a ninth NMOS, a tenth NMOS, and a third resistor. The bias circuit includes: a ninth PMOS, a tenth PMOS, an eleventh PMOS, an eleventh NMOS, a twelfth NMOS, a thirteenth NMOS, and a fourth resistor.

Abstract: A low-dropout regulator, including: a dynamic pole tracking circuit having an active load, a voltage-to-current converter, a current amplifier, a bias circuit, a regulating transistor, a first feedback resistor, a second feedback resistor, and a first capacitor. The dynamic pole tracking circuit includes: a first PMOS, a second PMOS, a first resistor, and a second resistor. The voltage-to-current converter includes: a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, a fifth NMOS, a sixth NMOS, a seventh NMOS, an eighth NMOS, a third PMOS, a fourth PMOS, a seventh PMOS, an eighth PMOS. The current amplifier includes: a fifth PMOS, a sixth PMOS, a ninth NMOS, a tenth NMOS, and a third resistor. The bias circuit includes: a ninth PMOS, a tenth PMOS, an eleventh PMOS, an eleventh NMOS, a twelfth NMOS, a thirteenth NMOS, and a fourth resistor.

Abstract: Methods of administering an oligonucleotide of interest into a cell in vitro or in vivo are described. In the methods, a small organic compound active agent is concurrently administered to the cell in an amount effective to increase the delivery of the oligonucleotide into the cell, and/or increase the activity of said oligonucleotide in the cell. Compositions useful for carrying out the method are also described.