Abstract: The provided is an on-chip voltage prediction circuit based on parameters of the chip's power delivery network. The circuit includes: an on-chip PDN impedance scanning module, an on-chip voltage monitoring module, an on-chip PDN parameter lookup table storage module, an on-chip predictive digital power meter, and an on-chip voltage prediction-calculation module. The circuit establishes a physical model that maps historical voltages and predicted current information to predicted voltage information. By quantizing the model and using the voltage monitoring circuit and the predictive digital power meter together, the provided implements on-chip deployment of the voltage prediction circuit, and effectively predicts future on-chip voltages.

Abstract: This application discloses a network management method. The method includes: receiving first request information, where the first request information is used to request whether to perform a management operation on a first subordinate closed-loop control process set of a closed-loop control process in addition to performing the management operation on the closed-loop control process, and the closed-loop control process is used to manage a network entity or a network service; and performing the management operation based on the first request information.

Abstract: In an embodiment of the disclosure, disclosed is a circuit based on in-memory computing in a digital domain, including: an array of computational storage cells, the computational storage cells including a preset number of data storage cells and a preset number of single-bit multipliers in one-to-one correspondence; an adder tree configured to accumulate products output by respective computational storage cells to obtain an accumulated result; and a multi-bit input transfer logic configured to convert accumulated results output by the adder tree and corresponding to respective single bits included in the input feature data into a multiply-accumulate result of multi-bit input feature data and multi-bit weight data. An in-memory multiply-accumulation is implemented or multi-bit weight data and input feature data, so that efficiency and energy efficiency density of in-memory computing is improved, “read disturb write” issue caused by a voltage change on bit lines is avoided, and computing stability is improved.

Abstract: A memory unit is controlled by a first word line and a second word line. The memory unit includes a memory cell and a transpose cell. The memory cell stores a weight. The memory cell is controlled by the first word line and includes a local bit line transmitting the weight. The transpose cell is connected to the memory cell and receives the weight via the local bit line. The transpose cell includes an input bit line, an input bit line bar, an output bit line and an output bit line bar. Each of the input bit line and the input bit line bar transmits a multi-bit input value, and the transpose cell is controlled by the second word line to generate a multi-bit output value on each of the output bit line and the output bit line bar according to the multi-bit input value and the weight.

Abstract: A memory unit is controlled by a first word line and a second word line. The memory unit includes a memory cell and a transpose cell. The memory cell stores a weight. The memory cell is controlled by the first word line and includes a local bit line transmitting the weight. The transpose cell is connected to the memory cell and receives the weight via the local bit line. The transpose cell includes an input bit line, an input bit line bar, an output bit line and an output bit line bar. Each of the input bit line and the input bit line bar transmits a multi-bit input value, and the transpose cell is controlled by the second word line to generate a multi-bit output value on each of the output bit line and the output bit line bar according to the multi-bit input value and the weight.

Abstract: A memory cell for computing-in-memory applications is controlled by a first bit line, a second bit line, a word line and a read word line. The read word line transmits an input value. The memory cell includes a plurality of read-decoupled cells. Each of the read-decoupled cells stores a weight and includes a first read-decoupled transistor and a second read-decoupled transistor. The first read-decoupled transistor has a first transistor width and is controlled by the weight. The second read-decoupled transistor has a second transistor width equal to the first transistor width and generates a read bit line signal according to the input value, the weight and the second transistor width. The second transistor width of the second read-decoupled transistor of one of the read-decoupled cells is two times larger than the second transistor width of the second read-decoupled transistor of another one of the read-decoupled cells.

Abstract: A multi-bit computing circuit for computing-in-memory applications is controlled by an input port and includes a memory cell array and a capacitor sharing unit. The memory cell array includes a plurality of memory cells connected to the input port. The memory cells store a weight which is formed in two's complement. The capacitor sharing unit includes a plurality of switches, a plurality of capacitors and a sense amplifier. The switches are electrically connected to the memory cells, respectively. The capacitors are electrically connected to the switches, respectively. The sense amplifier is electrically connected to the capacitors and generates a total operational value. The capacitors are located among the switches and the sense amplifier, and the switches are switched to enable the total operational value to be equal to the input value multiplied by the weight. The present disclosure utilizes 8T SRAM cells without an extra DAC structure.

Abstract: A grooming method and apparatus for a packet optical transport network are disclosed. The method includes: according to an arrangement order of various services, planning a path from a service source node to a service target node in an ith service in a topology set graph; when the path includes a wavelength link in a physical link, removing the wavelength link, and establishing a virtual link between a link source node and a link target node of the removed wavelength link; updating capacities of various links in the path; calculating a weight of a newly established virtual link, and adding the newly established virtual link and the corresponding weight to the topology set graph; and planning a path from a service source node to a service target node in an i+1th service in the topology set graph, until all services are finished.

Abstract: A grooming method and apparatus for a packet optical transport network are disclosed. The method includes: according to an arrangement order of various services, planning a path from a service source node to a service target node in an ith service in a topology set graph; when the path includes a wavelength link in a physical link, removing the wavelength link, and establishing a virtual link between a link source node and a link target node of the removed wavelength link; updating capacities of various links in the path; calculating a weight of a newly established virtual link, and adding the newly established virtual link and the corresponding weight to the topology set graph; and planning a path from a service source node to a service target node in an i+1th service in the topology set graph, until all services are finished.