Abstract: A method and device for monitoring a fault of a wind power generator set. The method includes the following steps: performing (101) fault identification on a component in a wind power generator set; and presenting (102) an identified fault using a three-dimensional model of the component. The device includes corresponding identifying module (61) and presenting module (62). By using the method and device, the fault monitor can intuitively observe the fault existed in the component, which not only is beneficial for taking effective fault processing measures before a minor fault evolves into a serious fault and thus reduces the harm of the fault, but also reduces the experience requirements for the fault monitor and avoids the process that the fault monitor in the prior art analyzes a two-dimensional curve to identify whether there is a fault in the component according to his experience.

Abstract: A method and device for monitoring a fault of a wind power generator set. The method includes the following steps: performing (101) fault identification on a component in a wind power generator set; and presenting (102) an identified fault using a three-dimensional model of the component. The device includes corresponding identifying module (61) and presenting module (62). By using the method and device, the fault monitor can intuitively observe the fault existed in the component, which not only is beneficial for taking effective fault processing measures before a minor fault evolves into a serious fault and thus reduces the harm of the fault, but also reduces the experience requirements for the fault monitor and avoids the process that the fault monitor in the prior art analyzes a two-dimensional curve to identify whether there is a fault in the component according to his experience.

Abstract: The disclosure includes a description of an apparatus having circuitry to determine a first hash value for a first packet tuple of a first packet traveling in a first direction of a duplex connection and determine a processor for the first packet from a set of multiple processors based, at least in part, on the first hash value. The apparatus includes circuitry to determine a second hash value for a second packet tuple of a second packet traveling in a second direction of the duplex connection and determine the same processor for the second packet from the set of multiple processors based, at least in part, on the second hash value.

Abstract: The disclosure includes a description of an apparatus having circuitry to determine a first hash value for a first packet tuple of a first packet traveling in a first direction of a duplex connection and determine a processor for the first packet from a set of multiple processors based, at least in part, on the first hash value. The apparatus includes circuitry to determine a second hash value for a second packet tuple of a second packet traveling in a second direction of the duplex connection and determine the same processor for the second packet from the set of multiple processors based, at least in part, on the second hash value.

Abstract: Checking for memory access collisions in a multiple processor architecture is described. Memory access collisions may be found by simulating an instruction to be executed by a multiple processor computing system in which the processors share memory access, extracting memory access information from the instruction, searching a virtual memory map for a memory access conflict, and reporting the conflict if a conflict is found in the search.

Abstract: The disclosure includes a description of an apparatus having circuitry to determine a first hash value for a first packet tuple of a first packet traveling in a first direction of a duplex connection and determine a processor for the first packet from a set of multiple processors based, at least in part, on the first hash value. The apparatus includes circuitry to determine a second hash value for a second packet tuple of a second packet traveling in a second direction of the duplex connection and determine the same processor for the second packet from the set of multiple processors based, at least in part, on the second hash value.

Abstract: Checking for memory access collisions in a multiple processor architecture is described. Memory access collisions may be found by simulating an instruction to be executed by a multiple processor computing system in which the processors share memory access, extracting memory access information from the instruction, searching a virtual memory map for a memory access conflict, and reporting the conflict if a conflict is found in the search.