Patents by Inventor Xinchao Wang
Xinchao Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11919067Abstract: A sand core structure for die-casting includes a positioning-filling rod and a sand core body configured to encompass the positioning-filling rod. The positioning-filling rod has a compressive strength greater than a compressive strength of the sand core body, and the positioning-filling rod is made of a breathable material.Type: GrantFiled: August 1, 2023Date of Patent: March 5, 2024Assignee: XIAMEN JJD MACHINERY CO., LTD.Inventors: Hualan Wang, Jialin Wang, Xinchao Tang
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Publication number: 20230064344Abstract: A fluorosilicone surfactant, and a preparation method and a use thereof are provided. The preparation method of the fluorosilicone surfactant includes: mixing alkynol or a derivative thereof, an allylpolyether, and an alkenyl fluorine-containing monomer with hydrogen-containing silicone oil to allow a hydrosilylation reaction, where a structural formula of the hydrogen-containing silicone oil includes at least three Si—H bonds. The fluorosilicone surfactant prepared by the present disclosure has both excellent wettability and low-foaming performance.Type: ApplicationFiled: November 18, 2019Publication date: March 2, 2023Applicant: Corechem Corporation Holding Co., LtdInventors: Xinchao WANG, Dawei XU, Fanwei MENG
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Patent number: 9794525Abstract: Systems and methods for tracking interacting objects may acquire, with a sensor, and two or more images associated with two or more time instances. A processor may generate image data from the two or more images. The processor may apply an extended Probability Occupancy Map (POM) algorithm to the image data to obtain probability of occupancy for a container class of potentially interacting objects, probability of occupancy for a containee class of the potentially interacting objects, and a size relationship of the potentially interacting objects, over a set of discrete locations on a ground plane for each time instance. The processor may estimate trajectories of an object belonging to each of the two classes by determining a solution of a tracking model on the basis of the occupancy probabilities and a set of rules describing the interaction between objects of different or the same classes.Type: GrantFiled: March 24, 2015Date of Patent: October 17, 2017Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)Inventors: Engin Turetken, Pascal Fua, Francois Fleuret, Xinchao Wang
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Publication number: 20170135674Abstract: Embodiments of the present invention relate to a wireless ultrasonic probe and an ultrasonic machine. The wireless ultrasonic probe comprises: a probe body for transmitting and receiving ultrasonic waves; and a heat sink comprising a first end portion and a second end portion, wherein at least a part of the second end portion is disposed within the probe body, and the first end portion is formed in a manner that the second end portion extends to the outside of the probe body. The wireless ultrasonic probe can efficiently dissipate heat generated thereby during charging and discharging operation procedures.Type: ApplicationFiled: March 2, 2015Publication date: May 18, 2017Inventors: Kevin Wang, Xinchao Wang
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Patent number: 9362214Abstract: A method for manufacturing a lead frame structure for semiconductor packaging. The method includes providing a metal substrate having a top surface and a back surface, forming a first photoresist film on the top surface of the metal substrate, forming a top surface etching pattern in the first photoresist film using photolithography, forming a second photoresist film on the back surface of the metal substrate, forming a back surface etching pattern in the second photoresist film using photolithography, performing an etching process on the top surface and the back surface of the metal substrate, removing the first photoresist film and the second photoresist film, placing the etched metal substrate in a mold, encapsulating the etched metal substrate using the mold; and performing a plating process on the encapsulated metal substrate.Type: GrantFiled: March 12, 2014Date of Patent: June 7, 2016Assignee: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO., LTD.Inventors: Xinchao Wang, Zhizhong Liang
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Patent number: 9252113Abstract: A no-exposed-pad ball grid array (BGA) packaging structure includes a metal substrate, a first die coupled to a top surface of the metal substrate, and a plurality of outer leads formed on the metal substrate and extending to the proximity of the die. A metal layer that contains a plurality of inner leads corresponding to the plurality of outer leads and extending to the proximity of the die is formed on the metal substrate by a multi-layer electrical plating process such that a lead pitch of the plurality of inner leads is significantly reduced. Furthermore, the die and the plurality of inner leads are connected by metal wires, and a plurality of solder balls is attached to a back surface of the plurality of outer leads and a die pad. The die, the plurality of inner leads, and the metal wires are sealed with a molding compound.Type: GrantFiled: April 22, 2014Date of Patent: February 2, 2016Assignee: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO., LTD.Inventors: Xinchao Wang, Zhizhong Liang
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Patent number: 9209117Abstract: A quad flat no-lead (QFN) packaging structure. The QFN packaging structure includes a metal substrate, a first die coupled to a top surface of the metal substrate, and a plurality of I/O pads formed on the metal substrate, and extending to the proximity of the die. The no-exposed-pad QFN packaging structure also includes a first metal layer containing a plurality of inner leads corresponding to the plurality of I/O pads and extending to proximity of the die and is formed on the metal substrate by a multi-layer electrical plating process. Further, the no-exposed-pad QFN packaging structure includes metal wires connecting the die and the plurality of inner leads, and a second metal layer formed on a back surface of the plurality of I/O pads.Type: GrantFiled: May 28, 2014Date of Patent: December 8, 2015Assignee: Jiangsu Changjiang Electronics Technology Co., Ltd.Inventors: Xinchao Wang, Zhizhong Liang
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Patent number: 9209115Abstract: A quad flat no-lead (QFN) packaging structure. The QFN packaging structure includes a metal substrate, a first outer die pad formed on the metal substrate, and a first die coupled to a top surface of the first outer die pad. The QFN packaging structure also includes a plurality of I/O pads formed on the metal substrate, and a first metal layer containing a plurality of inner leads corresponding to the plurality of I/O pads and extending to proximity of the die. The first metal layer is formed on the metal substrate by a multi-layer electrical plating process such that a lead pitch of the plurality of inner leads is significantly reduced. Further, the QFN packaging structure includes metal wires connecting die and the plurality of inner leads, and a second metal layer formed on a back surface of the plurality of I/O pads and the die pad.Type: GrantFiled: April 24, 2014Date of Patent: December 8, 2015Assignee: Jiangsu Changjiang Electronics Technology Co., Ltd.Inventors: Xinchao Wang, Zhizhong Liang
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Publication number: 20150281655Abstract: Systems and methods for tracking interacting objects may acquire, with a sensor, and two or more images associated with two or more time instances. A processor may generate image data from the two or more images. The processor may apply an extended Probability Occupancy Map (POM) algorithm to the image data to obtain probability of occupancy for a container class of potentially interacting objects, probability of occupancy for a containee class of the potentially interacting objects, and a size relationship of the potentially interacting objects, over a set of discrete locations on a ground plane for each time instance. The processor may estimate trajectories of an object belonging to each of the two classes by determining a solution of a tracking model on the basis of the occupancy probabilities and a set of rules describing the interaction between objects of different or the same classes.Type: ApplicationFiled: March 24, 2015Publication date: October 1, 2015Inventors: ENGIN TURETKEN, Pascal FUA, Francois FLEURET, Xinchao WANG
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Patent number: 9105622Abstract: A barrel-plating quad flat no-lead (QFN) package structure and a method for manufacturing the same. The method includes: providing a metal substrate for a plurality of QFN components; forming a first photoresist film on a top surface of the substrate; forming a plating pattern in the first photoresist film; forming a first metal layer containing a plurality of inner leads; etching the substrate from the back surface of the substrate to form a plurality of I/O pads; filling sealant in the etched areas; attaching at least one die in a predetermined region on the top surface of the substrate; connecting the die and the inner leads using metal wires; sealing the die, the inner leads, and the metal wires with a molding compound; separating the resulting joint QFN components into individual QFN components; and forming a second metal layer on the back surface of the I/O pads.Type: GrantFiled: May 6, 2014Date of Patent: August 11, 2015Assignee: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO., LTD.Inventors: Xinchao Wang, Zhizhong Liang
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Publication number: 20140332943Abstract: A barrel-plating quad flat no-lead (QFN) package structure and a method for manufacturing the same. The method includes: providing a metal substrate for a plurality of QFN components; forming a first photoresist film on a top surface of the substrate; forming a plating pattern in the first photoresist film; forming a first metal layer containing a plurality of inner leads; etching the substrate from the back surface of the substrate to form a plurality of I/O pads; filling sealant in the etched areas; attaching at least one die in a predetermined region on the top surface of the substrate; connecting the die and the inner leads using metal wires; sealing the die, the inner leads, and the metal wires with a molding compound; separating the resulting joint QFN components into individual QFN components; and forming a second metal layer on the back surface of the I/O pads.Type: ApplicationFiled: May 6, 2014Publication date: November 13, 2014Applicant: Jiangsu Changjiang Electronics Technology Co., Ltd.Inventors: Xinchao WANG, Zhizhong LIANG
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Publication number: 20140319664Abstract: A quad flat no-lead (QFN) packaging structure. The QFN packaging structure includes a metal substrate, a first outer die pad formed on the metal substrate, and a first die coupled to a top surface of the first outer die pad. The QFN packaging structure also includes a plurality of I/O pads formed on the metal substrate, and a first metal layer containing a plurality of inner leads corresponding to the plurality of I/O pads and extending to proximity of the die. The first metal layer is formed on the metal substrate by a multi-layer electrical plating process such that a lead pitch of the plurality of inner leads is significantly reduced. Further, the QFN packaging structure includes metal wires connecting die and the plurality of inner leads, and a second metal layer formed on a back surface of the plurality of I/O pads and the die pad.Type: ApplicationFiled: April 24, 2014Publication date: October 30, 2014Applicant: Jiangsu Changjiang Electronics Technology Co., Ltd.Inventors: Xinchao WANG, Zhizhong LIANG
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Publication number: 20140312476Abstract: A no-exposed-pad ball grid array (BGA) packaging structure includes a metal substrate, a first die coupled to a top surface of the metal substrate, and a plurality of outer leads formed on the metal substrate and extending to the proximity of the die. A metal layer that contains a plurality of inner leads corresponding to the plurality of outer leads and extending to the proximity of the die is formed on the metal substrate by a multi-layer electrical plating process such that a lead pitch of the plurality of inner leads is significantly reduced. Furthermore, the die and the plurality of inner leads are connected by metal wires, and a plurality of solder balls is attached to a back surface of the plurality of outer leads and a die pad. The die, the plurality of inner leads, and the metal wires are sealed with a molding compound.Type: ApplicationFiled: April 22, 2014Publication date: October 23, 2014Applicant: Jiangsu Changjiang Electronics Technology Co., Ltd.Inventors: Xinchao WANG, Zhizhong LIANG
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Publication number: 20140264795Abstract: A quad flat no-lead (QFN) packaging structure. The QFN packaging structure includes a metal substrate, a first die coupled to a top surface of the metal substrate, and a plurality of I/O pads formed on the metal substrate, and extending to the proximity of the die. The no-exposed-pad QFN packaging structure also includes a first metal layer containing a plurality of inner leads corresponding to the plurality of I/O pads and extending to proximity of the die and is formed on the metal substrate by a multi-layer electrical plating process. Further, the no-exposed-pad QFN packaging structure includes metal wires connecting the die and the plurality of inner leads, and a second metal layer formed on a back surface of the plurality of I/O pads.Type: ApplicationFiled: May 28, 2014Publication date: September 18, 2014Applicant: Jiangsu Changjiang Electronics Technology Co., Ltd.Inventors: Xinchao WANG, Zhizhong LIANG
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Publication number: 20140191384Abstract: A method for manufacturing a lead frame structure for semiconductor packaging. The method includes providing a metal substrate having a top surface and a back surface, forming a first photoresist film on the top surface of the metal substrate, forming a top surface etching pattern in the first photoresist film using photolithography, forming a second photoresist film on the back surface of the metal substrate, forming a back surface etching pattern in the second photoresist film using photolithography, performing an etching process on the top surface and the back surface of the metal substrate, removing the first photoresist film and the second photoresist film, placing the etched metal substrate in a mold, encapsulating the etched metal substrate using the mold; and performing a plating process on the encapsulated metal substrate.Type: ApplicationFiled: March 12, 2014Publication date: July 10, 2014Applicant: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO., LTD.Inventors: Xinchao WANG, Zhizhong LIANG
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Publication number: 20080315412Abstract: The invention discloses a novel package structure of integrate circuit or discrete device and packaging method, and includes the lead pins adjacent to the island; another metal layer formed at the bottom of the island; another metal layer formed at the bottom of lead pins; chip mounted on the island; wires bonded between the chip and the lead pins; the molded body encapsulating the top surface and side surface of the island and the lead pins, small protrusions of the island and the lead pins below the molded body; in the individual package, the number of the island can be one or more, lead pins can be arrayed at one side of the island, also can be arrayed at two sides or three sides of the island, one or two rows of lead pins can be located around the island. The invention provides strong welding, good quality, low cost, smooth production, wide applicability, flexible arrangement of the chips.Type: ApplicationFiled: April 6, 2006Publication date: December 25, 2008Applicant: Jiangsu Changjiang Electronics Technology Co., LtdInventors: Jerry Liang, Jieren Xie, Xinchao Wang, Xiekang Yu, Yujuan Tao, Rongfu Wen, Fushou Li, Zhengwei Zhou, Da Wang, Haibo Ge, Qiang Zheng, Zhen Gong, Weijun Yang
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Publication number: 20080285251Abstract: A packaging substrate with fiat bumps for an electronic device and a method of manufacturing the same relate to the production of the packaging substrate for an electronic device, which comprises base islands and pins structurally and wherein the base islands and pins which all exhibit flat bump shape distribute on the front face of the substrate; the bottom side of the bumps, namely the rear faces of the base islands and pins are contiguous in the same substrate; in the packaging body of a single electronic device to be formed in later procedure, one or more base island may be included, the pins may arrange on one single side of the base island, also may arrange on the both sides or three sides of the base island, or may surround the base island so as to form the structure of one or more circuits of pins.Type: ApplicationFiled: April 6, 2006Publication date: November 20, 2008Applicant: Jiangsu Changiang Electronics Technology Co., Ltd.Inventors: Jerry Liang, Jieren Xie, Xinchao Wang, Xiekang Yu, Yujuan Tao, Rongfu Wen, Fushou Li, Zhengwei Zhou, Da Wang, Haibo Ge, Qiang Zheng, Zhen Gong, Weijun Yang
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Publication number: 20080258273Abstract: The invention discloses an ultra thin package structure of leadless electronic device and the packaging method, and includes lead support base adjacent to the chip support base; chip mounted on the chip support base; wires bonded between chip and lead support base; the molded body encapsulating the top surface and side surface of the chip support base, small protrusions of the chip support base and lead support base below the molded body; in the individual package, the number of the chip support base island can be one or more, the lead pins can be arrayed at one side of the island, also can be arrayed at two sides or three sides of the island, one or two rows of lead pins can be located around the island.Type: ApplicationFiled: April 6, 2006Publication date: October 23, 2008Applicant: Jiangsu Changjiang Electronics Technology Co., LtdInventors: Jerry Liang, Jieren Xie, Xinchao Wang, Xiekang Yu, Yujuan Tao, Rongfu Wen, Fushou Li, Zhengwei Zhou, Da Wang, Haibo Ge, Qiang Zheng, Zhen Gong, Weijun Yang