Abstract: A method for semiconductor processing is provided wherein a workpiece having an underlying body and a plurality of features extending therefrom, is provided. A first set of the plurality of features extend from the underlying body to a first plane, and a second set of the plurality features extend from the underlying body to a second plane. A protection layer overlies each of the plurality of features and an isolation layer overlies the underlying body and protection layer, wherein the isolation has a non-uniform first oxide density associated therewith. The isolation layer anisotropically etched based on a predetermined pattern, and then isotropically etched, wherein a second oxide density of the isolation layer is substantially uniform across the workpiece. The predetermined pattern is based, at least in part, on a desired oxide density, a location and extension of the plurality of features to the first and second planes.

Abstract: A buried layer architecture which includes a floating buried layer structure adjacent to a high voltage buried layer connected to a deep well of the same conductivity type for components in an IC is disclosed. The floating buried layer structure surrounds the high voltage buried layer and extends a depletion region of the buried layer to reduce a peak electric field at lateral edges of the buried layer. When the size and spacing of the floating buried layer structure are optimized, the well connected to the buried layer may be biased to 100 volts without breakdown. Adding a second floating buried layer structure surrounding the first floating buried layer structure allows operation of the buried layer up to 140 volts. The buried layer architecture with the floating buried layer structure may be incorporated into a DEPMOS transistor, an LDMOS transistor, a buried collector npn bipolar transistor and an isolated CMOS circuit.

Abstract: A method of forming integrated circuits (IC) having at least one metal insulator metal (MIM) capacitor. A bottom electrode is formed on a predetermined region of a semiconductor surface of a substrate. At least one dielectric layer including silicon is formed on the bottom electrode, wherein a thickness of the dielectric layer is <1,000 A. A top electrode layer is formed on the dielectric layer. A patterned masking layer is formed on the top electrode layer. Etching using dry-etching at least in part is used to etch the top electrode layer outside the patterned masking layer to reach the dielectric layer, which removes ?100 A of the thickness of the dielectric layer. The dry etch process includes using a first halogen comprising gas, a second halogen comprising gas that comprises fluorine, and a carrier gas.

Abstract: A method of forming integrated circuits (IC) having at least one metal insulator metal (MIM) capacitor. A bottom electrode is formed on a predetermined region of a semiconductor surface of a substrate. At least one dielectric layer including silicon is formed on the bottom electrode, wherein a thickness of the dielectric layer is <1,000 A. A top electrode layer is formed on the dielectric layer. A patterned masking layer is formed on the top electrode layer. Etching using dry-etching at least in part is used to etch the top electrode layer outside the patterned masking layer to reach the dielectric layer, which removes ?100 A of the thickness of the dielectric layer. The dry etch process includes using a first halogen comprising gas, a second halogen comprising gas that comprises fluorine, and a carrier gas.

Abstract: A buried layer architecture which includes a floating buried layer structure adjacent to a high voltage buried layer connected to a deep well of the same conductivity type for components in an IC is disclosed. The floating buried layer structure surrounds the high voltage buried layer and extends a depletion region of the buried layer to reduce a peak electric field at lateral edges of the buried layer. When the size and spacing of the floating buried layer structure are optimized, the well connected to the buried layer may be biased to 100 volts without breakdown. Adding a second floating buried layer structure surrounding the first floating buried layer structure allows operation of the buried layer up to 140 volts. The buried layer architecture with the floating buried layer structure may be incorporated into a DEPMOS transistor, an LDMOS transistor, a buried collector npn bipolar transistor and an isolated CMOS circuit.

Abstract: A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom electrodes (140, 144) and a nonconductive capacitor dielectric (142). In one example, the dielectric (142) includes first and second thin dielectric layers (112, 114) that sandwich a layer of antireflective material (118). The thin layers (112, 114) provide the dielectric behavior necessary for the capacitor while the antireflective layer (118) promotes reduced feature sizes by mitigating reflected standing waves, among other things.

Abstract: A method for semiconductor processing is provided wherein a workpiece having an underlying body and a plurality of features extending therefrom, is provided. A first set of the plurality of features extend from the underlying body to a first plane, and a second set of the plurality features extend from the underlying body to a second plane. A protection layer overlies each of the plurality of features and an isolation layer overlies the underlying body and protection layer, wherein the isolation has a non-uniform first oxide density associated therewith. The isolation layer anisotropically etched based on a predetermined pattern, and then isotropically etched, wherein a second oxide density of the isolation layer is substantially uniform across the workpiece. The predetermined pattern is based, at least in part, on a desired oxide density, a location and extension of the plurality of features to the first and second planes.

Abstract: A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom electrodes (140, 144) and a nonconductive capacitor dielectric (142). In one example, the dielectric (142) includes first and second thin dielectric layers (112, 114) that sandwich a layer of antireflective material (118). The thin layers (112, 114) provide the dielectric behavior necessary for the capacitor while the antireflective layer (118) promotes reduced feature sizes by mitigating reflected standing waves, among other things.

Abstract: A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom electrodes (140, 144) and a nonconductive capacitor dielectric (142). In one example, the dielectric (142) includes first and second thin dielectric layers (112, 114) that sandwich a layer of antireflective material (118). The thin layers (112, 114) provide the dielectric behavior necessary for the capacitor while the antireflective layer (118) promotes reduced feature sizes by mitigating reflected standing waves, among other things.

Abstract: The present invention provides a method for monitoring a shift in a buried layer in a semiconductor device. The method for monitoring the shift in the buried layer, among other steps, includes forming a buried layer test structure in, on or over a substrate of a semiconductor device, the buried layer test structure including a first test buried layer located in or on the substrate, the first test buried layer shifted a predetermined distance with respect to a first test feature. The buried layer test structure further includes a second test buried layer lodated in the substrate, the second test buried layer shifted a predetermined but different distance with respect to a second test feature. The method for monitoring the shift in the buried layer may further include applying a test signal to the buried layer test structure to determine an actual shift relative to the predetermined shift.

Abstract: A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom electrodes (140, 144) and a nonconductive capacitor dielectric (142). In one example, the dielectric (142) includes first and second thin dielectric layers (112, 114) that sandwich a layer of antireflective material (118). The thin layers (112, 114) provide the dielectric behavior necessary for the capacitor while the antireflective layer (118) promotes reduced feature sizes by mitigating reflected standing waves, among other things.

Abstract: The present invention provides a method for monitoring a shift in a buried layer in a semiconductor device and a method for manufacturing an integrated circuit using the method for monitoring the shift in the buried layer. The method for monitoring the shift in the buried layer, among other steps, includes forming a buried layer test structure (200) in, on or over a substrate (210) of a semiconductor device, the buried layer test structure (200) including a first test buried layer (230a) located in or on the substrate (210), the first test buried layer (230a) shifted a predetermined distance with respect to a first test feature (240a). The buried layer test structure (200) further includes a second test buried layer (230b) located in the substrate (210), the second test buried layer (23b) shifted a predetermined but different distance with respect to a second test feature (240b).