Abstract: A scalable hardware accelerator configured to compute video quality metrics is disclosed. In some embodiments, an accelerator for video quality metrics comprises an application-specific integrated circuit that includes a buffer memory configured to store at least a portion of a reference frame of a video and at least a corresponding portion of a distorted frame of a transcoded version of the video and that includes a processing unit configured to receive data from the buffer memory and compute a perception-based video quality metric for the distorted frame with respect to the reference frame.

Abstract: A disclosed computer-implemented method may include (1) selecting, from a video stream, a reference frame and a current frame, (2) collecting a reference histogram of the reference frame and a current histogram of the current frame, and (3) generating a smoothed reference histogram by applying a smoothing function to at least a portion of the reference histogram. In some examples, the computer-implemented method may also include (1) determining a similarity metric between the smoothed reference histogram and the current histogram and, (2) when the similarity metric is greater than a threshold value, applying weighted prediction during a motion estimation portion of an encoding of the video stream. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Various features of a high performance hardware scaler are disclosed herein. In some embodiments, a hardware scaler comprises a first processing unit configured to perform preparation and scaling operations and a second processing unit configured to perform preparation and scaling operations. The first processing unit and the second processing unit alternatively switch between performing preparation and scaling operations when processing a current input pixel block such that the first processing unit performs scaling operations while the second processing unit performs preparation operations and the second processing unit performs scaling operations while the first processing unit performs preparation operations.

Abstract: A disclosed computer-implemented method may include (1) selecting, from a video stream, a reference frame and a current frame, (2) collecting a reference histogram of the reference frame and a current histogram of the current frame, and (3) generating a smoothed reference histogram by applying a smoothing function to at least a portion of the reference histogram. In some examples, the computer-implemented method may also include (1) determining a similarity metric between the smoothed reference histogram and the current histogram and, (2) when the similarity metric is greater than a threshold value, applying weighted prediction during a motion estimation portion of an encoding of the video stream. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A scalable hardware accelerator configured to compute video quality metrics is disclosed. In some embodiments, an accelerator for video quality metrics comprises an application-specific integrated circuit that includes an interface configured to receive pixel data of a frame of a video being analyzed for quality metric determination and a kernel configured to compute a video quality metric for the received pixel data using a fixed-point hardware approximation of a floating-point based algorithm associated with the video quality metric.

Abstract: A scalable hardware accelerator configured to compute video quality metrics is disclosed. In some embodiments, an accelerator for video quality metrics comprises an application-specific integrated circuit that includes a buffer memory configured to store at least a portion of a reference frame of a video and at least a corresponding portion of a distorted frame of a transcoded version of the video and that includes a processing unit configured to receive data from the buffer memory and compute a perception-based video quality metric for the distorted frame with respect to the reference frame.

Abstract: The disclosed may include various systems and methods for improving the efficiency and scalability of large-scale systems. For example, the disclosed may include systems and methods for automatic privacy enforcement using privacy-aware infrastructure, scalable general-purpose low cost integer motion search, efficient scaler filter coefficients layout for flexible scaling quality control with limited hardware resources, hardware optimization for power saving with both different codecs enabled, optimizing storage overhead and performance for large distributed data warehouse, mass and volume efficient integration of intersatellite link terminals to a satellite bus, and overcoming retention limit for memory-based distributed database systems.

Abstract: Systems and methods for performing native command queuing according to the protocol specified by Serial ATA II for transferring data between a disk and system memory are described. Native command queuing context for queued commands is maintained by a host controller device driver and is provided to the host controller as needed to process the queued commands. The host controller is simplified since it only stores the context of the one command being processed. The host controller generates a backoff interrupt when a command cannot be queued. The host controller generates a DMA transfer context request interrupt to request programming of the registers that store the context for the one command being processed.

Abstract: Systems and methods for performing native command queuing according to the protocol specified by Serial ATA II for transferring data between a disk and system memory are described. Native command queuing context for queued commands is maintained by a host controller device driver and is provided to the host controller as needed to process the queued commands. The host controller is simplified since it only stores the context of the one command being processed. The host controller generates a backoff interrupt when a command cannot be queued. The host controller generates a DMA transfer context request interrupt to request programming of the registers that store the context for the one command being processed.