Abstract: A false-trigger free power-rail ESD clamp protection circuit includes an ESD impact detection component, a discharge transistor, a discharge transistor turn-on channel, and a discharge transistor shutoff channel. The circuit, in a smaller layout area, has very strong electrostatic charge discharge capability under ESD impact, little power leakage during normal power-up, and relatively strong false-trigger immunity capability for quick power-up.

Abstract: The present invention provides a thermal management system, an X-ray detection device and a CT apparatus. The thermal management system comprises a heater, an air mixing portion and a fan. The heater is provided at an air inlet of the air mixing portion. The air mixing portion provides an air mixing space for mixing exterior air that enters the air mixing portion with interior air of the air mixing portion. The fan is provided at an air outlet of the air mixing portion, and supplies the mixed air in the air mixing portion to a target object to be thermally managed. Therefore, a response time of the thermal management system to operate for an external temperature change may be lengthened, thus occurrence of abrupt change in a temperature of the target object as the external temperature changes abruptly may be avoided, improving a reliability of the thermal management system.

Abstract: Disclosed herein is a method for isolating active regions in a germanium-based MOS device. A surface of a germanium-based substrate is covered by a thin polysilicon layer or a poly-SiGe layer, and an isolation structure of germanium dioxide covered by a silicon dioxide layer or a SiGe oxide layer on top is formed by means of two steps of oxidation in a case of the active regions are protected. Such two steps of oxidation using the polysilicon layer or the poly-SiGe layer as a sacrificial layer is advantageous to improve the isolation quality of a fabricated germanium dioxide and to reduce a beak effect occurred during a local field oxygen oxidation so as to dramatically elevate the performance of the germanium device.

Abstract: The present disclosure provides a genetically-modified probiotic expressing recombinent phenylalanine ammonia Lyase (PAL) useful for treating phenylketonuria.

Abstract: A permanent magnet motor has a rotor and a stator. The rotor has a shaft, a rotor core and commutator fixed to the shaft, and rotor windings wound about poles of the rotor core and electrically connected to the commutator. The stator has an axially extending round housing, a ring magnet member fixed to an inner surface of the round housing, an endcap, and at least one pair of brushes in sliding contact with the commutator. A chamber is formed by the housing and the endcap. The commutator is disposed in the chamber. A window lift device incorporating the motor is also provided.

Abstract: Congruent power and timing signals in a single electronic device. In an embodiment, a circuit may include just one isolation transformer operable to generate a power signal and a timing signal. On the secondary side, two branches may extract both a power signal and a clock signal for use in the circuit on the isolated secondary side. The first branch may be coupled to the transformer and operable to manipulate the signal into a power signal, such as a 5V DC signal. Likewise, the second circuit branch is operable to manipulate the signal into a clock signal, such as a 5 V signal with a frequency of 1 MHz. By extracting both a power supply signal and a clock signal from the same isolation transformer on the secondary side, valuable space may be saved on an integrated circuit device with only having a single winding for a single isolation transformer.

Abstract: A method for predicting a reliable lifetime of a SOI MOSFET device including: measuring a relationship of a gate resistance of the device varying as a function of a temperature at different wafer temperatures; performing a lifetime accelerating test on the device at different wafer temperatures, so as to obtain a degenerating relationship of a parameter representing the lifetime of the device as a function of stress time, and obtain a lifetime in the presence of self-heating when the parameter degenerates to 10%; performing a self-heating correction on the measured lifetime of the device by using the measured self-heating temperature and an Arrhenius model, so as to obtain a lifetime without self-heating influence; performing a self-heating correction on a variation of the drain current caused by self-heating; performing a self-heating correction on an impact ionization rate caused by hot carriers; and predicting the lifetime of the device under a bias.

Abstract: The present invention discloses a method for processing a gate dielectric layer deposited on a germanium-based or Group III-V compound-based substrate, belonging to a semiconductor device field. The method comprises the steps of depositing a high-K gate dielectric layer on the germanium-based or Group III-V compound-based substrate, and then performing a plasma process to the high-K gate dielectric layer by using fluorine plasma, wherein during the plasma process, a guiding electric field is applied so that fluorine ions, when being accelerated to a surface of the gate dielectric layer, has an energy of 5-50 eV and the fluorine plasma drifts into the high-K gate dielectric layer, a ratio of a density of the fluorine ions in the high-K gate dielectric layer and a density of oxygen atoms in the high-K gate dielectric layer being 0.01-0.15:1.

Abstract: In a non-planar based semiconductor process where the structure includes both N and P type raised structures (e.g., fins), and where a different type of epitaxy is to be grown on each of the N and P type raised structures, prior to the growing, a lithographic blocking material over one of the N and P type raised structure portions is selectively etched to expose and planarize a gate cap. After the first type of epitaxy is grown, the process is repeated for the other of the N and P type epitaxy.

Abstract: Disclosed herein is a method for isolating active regions in a germanium-based MOS device. A surface of a germanium-based substrate is covered by a thin polysilicon layer or a poly-SiGe layer, and an isolation structure of germanium dioxide covered by a silicon dioxide layer or a SiGe oxide layer on top is formed by means of two steps of oxidation in a case of the active regions are protected. Such two steps of oxidation using the polysilicon layer or the poly-SiGe layer as a sacrificial layer is advantageous to improve the isolation quality of a fabricated germanium dioxide and to reduce a beak effect occurred during a local field oxygen oxidation so as to dramatically elevate the performance of the germanium device.

Abstract: Disclosed is a liquid crystal compound. The compound has a general structural formula as shown by formula I. Such a compound has good thermal and UV stability, large positive dielectric anisotropy ??, and can achieve a low threshold voltage when used in optics, thereby having great significance to the fast response of display devices, and therefore being very suitable for formulating a liquid crystal mixture. A liquid crystal mixture containing such a liquid crystal unit can be applied to various display devices, and is especially suitable for TN-TFT and STN display devices, but can also be used in IPS (in-plane switching) and VA (vertically aligned) display devices.

Abstract: A multi-granularity parallel storage system including a plurality of memories, a shift generator, an address increment lookup unit, an address shifter, a row address generator, and a plurality of address adders. The shift generator is configured to generate a shift value. The address increment lookup unit is configured to generate input data for the address shifter. The address shifter is configured to cyclically shift the input data rightward by Shift elements and then output the shifted data. The row address generator is configured to generate a row address RowAddr and input the generated row address RowAddr to the other input terminal of each address adder. Each address adder is configured to perform a non-sign addition of the input data at the two input terminals to obtain a read/write (R/W) address for one of the memories and input the R/W address to an address input terminal of the memory.

Abstract: A CMOS device for reducing a radiation-induced charge collection and a method for fabricating the same. In the CMOS device, a heavily doped charge collection-suppressed region is disposed directly under the source region and the drain region. The region has a doping type opposite that of the source region and the drain region, and has a doping concentration not less than that of the source region and the drain region. The charge collection-suppressed region has a lateral part slightly less than or equal to that of the source region and the drain region, and has a lateral range toward to the channel not exceed the edges of the source region and the drain region. The CMOS device may greatly reduce a range of the funnel that appears under the action of a single particle, so that charges collected instantaneously under a force of an electric field may be reduced.

Abstract: This invention relates to liquid crystal compound of formula I containing a difluoromethyleneoxy linking group that hydrogen substituted by deuterium and therefore being very suitable for formulating a liquid crystal mixture. A liquid crystal mixture containing such type of liquid crystal compounds can be applied in various display devices.

Abstract: This invention relates to liquid crystal compound of formula I containing benzene derivatives group that hydrogen substituted by deuterium. Liquid crystal compounds of formula I have not only large positive dielectric anisotropy, but also moderate optical anisotropy and driving voltage, thereby having great significance to formulate a liquid crystal mixture. A liquid crystal mixture containing such type of liquid crystal compounds can be applied in various display devices, which is particularly suitable for TN and STN display devices, and can also be used in IPS and VA display devices.

Abstract: The embodiments of the present invention provide a Ge-based NMOS device structure and a method for fabricating the same. By using the method, double dielectric layers of germanium oxide (GeO2) and metal oxide are deposited between the source/drain region and the substrate. The present invention not only reduces the electron Schottky barrier height of metal/Ge contact, but also improves the current switching ratio of the Ge-based Schottky and therefore, it will improve the performance of the Ge-based Schottky NMOS transistor. In addition, the fabrication process is very easy and completely compatible with the silicon CMOS process. As compared with conventional fabrication method, the Ge-based NMOS device structure and the fabrication method in the present invention can easily and effectively improve the performance of the Ge-based Schottky NMOS transistor.

Abstract: Described herein is a technology for facilitating analysis of performance indicators. In accordance with one aspect, a hierarchical structure with a node representing a performance indicator is configured. Such configuration may include mapping one or more lowest level nodes to one or more data models for retrieving transactional data. In addition, one or more internal nodes of the hierarchical structure may be configured, including mapping the one or more internal nodes to one or more corresponding child nodes. The configuration data generated by such configuration may then be stored in a database for subsequent retrieval to generate a report.

Abstract: The present invention discloses a testing structure and method for interface trap density of gate oxide, relating to the field of quality and reliability researches of MOS devices. The present invention makes the interface traps density tests for gate oxide layers of n-type and p-type MOS devices completed on a same testing structure, this does not only shorten the measurement period by half but also decrease the costs for testing instruments, because the present testing method is based on a simple current-voltage scanning test without using equipments such as pulse generator required in conventional method. The testing results obtained according to the present invention are featured with spectral peak, which facilitates the data analysis and computation.

Abstract: The embodiments of the present invention provide a Ge-based NMOS device structure and a method for fabricating the same. By using the method, double dielectric layers of germanium oxide (GeO2) and metal oxide are deposited between the source/drain region and the substrate. The present invention not only reduces the electron Schottky barrier height of metal/Ge contact, but also improves the current switching ratio of the Ge-based Schottky and therefore, it will improve the performance of the Ge-based Schottky NMOS transistor. In addition, the fabrication process is very easy and completely compatible with the silicon CMOS process. As compared with conventional fabrication method, the Ge-based NMOS device structure and the fabrication method in the present invention can easily and effectively improve the performance of the Ge-based Schottky NMOS transistor.

Abstract: The present invention discloses a strained channel field effect transistor and a method for fabricating the same. The field effect transistor comprises a substrate, a source/drain, a gate dielectric layer, and a gate, characterized in that, an “L” shaped composite isolation layer, which envelops a part of a side face of the source/drain adjacent to a channel and the bottom of the source/drain, is arranged between the source/drain and the substrate; the composite isolation layer is divided into two layers, that is, an “L” shaped insulation thin layer contacting directly with the substrate and an “L” shaped high stress layer contacting directly with the source and the drain. The field effect transistor of such a structure improves the mobility of charge carriers by introducing stress into the channel by means of the high stress layer, while fundamentally improving the device structure of the field effect transistor and improving the short channel effect suppressing ability of the device.