Patents by Inventor Xingchong Gu

Xingchong Gu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240290828
    Abstract: Techniques for reducing peak on-state voltage of a semiconductor device fabricated in a wafer. A substrate layer is provided. An isolation structure is provided to laterally isolate the semiconductor device from other semiconductor devices in the wafer. A tub structure is formed in the substrate layer. A base layer is provided such that the base layer is disposed under the substrate layer. The base layer includes an anode having an associated active region that includes a drift region in the substrate layer. The tub structure is disposed inside the active region such that presence of the tub structure reduces a thickness of the drift region.
    Type: Application
    Filed: January 29, 2024
    Publication date: August 29, 2024
    Applicant: Littelfuse Semiconductor (Wuxi) Co., Ltd.
    Inventors: Xingchong Gu, Jifeng Zhou
  • Publication number: 20240258099
    Abstract: Techniques for plating a wafer with electrical glass during fabrication of semiconductor devices in the wafer. An electrical-conductivity network is formed in the wafer by doping a surface region of an isolation structure of the wafer. The isolation structure laterally isolates the semiconductor devices from one another in the wafer. After forming the electrical-conductivity network in the wafer, a glass deposition of a respective plating is formed atop each of one or more plating regions of the wafer.
    Type: Application
    Filed: January 29, 2024
    Publication date: August 1, 2024
    Applicant: Littelfuse Semiconductor (Wuxi) Co., Ltd.
    Inventors: Xingchong Gu, Jifeng Zhou, Lei He
  • Publication number: 20240096527
    Abstract: A transient voltage suppression (TVS) device and method of formation. A TVS device may include a first layer, disposed on a first surface of a substrate, comprising a first P+ layer; a second layer, disposed on a second surface of the substrate, opposite the first surface, comprising a second P+ layer; a third layer, disposed between the first P+ layer and the second P+ layer, comprising an N? layer; and an isolation diffusion region, comprising a P structure, connected to the second P+ layer, and extending along a perimeter of the N? layer.
    Type: Application
    Filed: September 15, 2023
    Publication date: March 21, 2024
    Applicant: Littelfuse Semiconductor (Wuxi) Co., Ltd.
    Inventors: Boris Rosensaft, Stefan Steinhoff, Xingchong Gu
  • Publication number: 20240096869
    Abstract: A transient voltage suppression (TVS) device. The TVS device may include a substrate, comprising a polarity of a first type. The TVS device may further include a first dopant layer, disposed on a first surface of the substrate, the first layer comprising a polarity of a second type, wherein the first dopant layer forms a P/N junction with the substrate. The TVS device may include a first buffer layer, disposed on the first dopant layer, and a first outer contact layer, disposed on the first buffer layer.
    Type: Application
    Filed: September 15, 2023
    Publication date: March 21, 2024
    Applicant: Littelfuse Semiconductor (Wuxi) Co., Ltd.
    Inventors: Lei Shi, Jifeng Zhou, Xingchong Gu