Abstract: This invention relates to liquid crystal compound of formula I containing a difluoromethyleneoxy linking group that hydrogen substituted by deuterium and therefore being very suitable for formulating a liquid crystal mixture. A liquid crystal mixture containing such type of liquid crystal compounds can be applied in various display devices.

Abstract: The present disclosure provides a processor having polymorphic instruction set architecture. The processor comprises a scalar processing unit, at least one polymorphic instruction processing unit, at least one multi-granularity parallel memory and a DMA controller. The polymorphic instruction processing unit comprises at least one functional unit. The polymorphic instruction processing unit is configured to interpret and execute a polymorphic instruction and the functional unit is configured to perform specific data operation tasks. The scalar processing unit is configured to invoke the polymorphic instruction and inquire an execution state of the polymorphic instruction. The DMA controller is configured to transmit configuration information for the polymorphic instruction and transmit data required by the polymorphic instruction to the multi-granularity parallel memory.

Abstract: Disclosed is a liquid crystal compound. The compound has a general structural formula as shown by formula I. Such a compound has good thermal and UV stability, large positive dielectric anisotropy ??, and can achieve a low threshold voltage when used in optics, thereby having great significance to the fast response of display devices, and therefore being very suitable for formulating a liquid crystal mixture. A liquid crystal mixture containing such a liquid crystal unit can be applied to various display devices, and is especially suitable for TN-TFT and STN display devices, but can also be used in IPS (in-plane switching) and VA (vertically aligned) display devices.

Abstract: The present invention discloses a method for extracting a trap time constant of a gate dielectric layer in a semiconductor device, which is related to the reliability of microelectronic devices. The method comprises initializing a state of a trap in the semiconductor device so that the trap finally comes to an empty state; applying a DC or AC signal to a gate terminal and a zero bias Vd1 to a drain terminal; after a period of time t1, applying small voltages Vg2 and Vd2 to the gate and drain terminals respectively, and detecting a state of a drain current Id; modifying the time t1 to t2=t1+?t while maintaining other conditions; repeatedly performing the previous steps in a same manner to perform N times of measurements for N numbers of time points t1, t1+?t, . . .

Abstract: The present invention discloses a preparation method of a germanium-based Schottky junction, comprising, cleaning a surface of N-type germanium-based substrate, then depositing a layer of CeO2 on the surface, and further depositing a layer of metal. The stability Ce—O—Ge bonds can be formed at the interface after rare earth oxides CeO2 are in contact with the germanium substrate, and this is beneficial to reduce the interface state density, improve the quality of the interface, and reduce the MIGS and suppress Fermi-level pinning. Meanwhile, the tunneling resistance introduced by CeO2 between the metal and the germanium substrate is smaller relative to the case of Si3N4, Al2O3, Ge3N4 or the like. In view of the excellent surface characteristics and small conduction band offset relative to the germanium substrate, interposing of the CeO2 dielectric layer is applicable to the preparation the germanium-based Schottky junction having a low resistivity.

Abstract: The present invention discloses a method for processing a gate dielectric layer deposited on a germanium-based or Group III-V compound-based substrate, belonging to a semiconductor device field. The method comprises the steps of depositing a high-K gate dielectric layer on the germanium-based or Group III-V compound-based substrate, and then performing a plasma process to the high-K gate dielectric layer by using fluorine plasma, wherein during the plasma process, a guiding electric field is applied so that fluorine ions, when being accelerated to a surface of the gate dielectric layer, has an energy of 5-50 eV and the fluorine plasma drifts into the high-K gate dielectric layer, a ratio of a density of the fluorine ions in the high-K gate dielectric layer and a density of oxygen atoms in the high-K gate dielectric layer being 0.01-0.15:1.

Abstract: A transient-triggered DC voltage-sustained power-rail ESD clamp circuit comprises: a transient-triggered module, a DC voltage-triggered module and a discharge device, wherein the transient-triggered module is connected with the DC voltage-triggered module and the discharge device respectively. When an ESD event is approaching, the ESD protection circuit can be turned on well and quickly, and can effectively avoid the problems of erroneous triggering and latching-up caused by quick power-on and high-frequency noise at the same time.

Abstract: A flexible seal for use in a solid oxide fuel cell stack is formed from a fiber matrix with a plurality of solid particles through tape casting method. The fibers and particles are preferably ceramic and may be formed from alumina or zirconia. The seal may be formed by forming a slurry of fibers, particles, a binder and a non-aqueous solvent, tape casting the slurry, drying the tape seal, die-cutting, prior to installation in the fuel cell stack.

Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.

Abstract: The present invention discloses a testing structure and method for interface trap density of gate oxide, relating to the field of quality and reliability researches of MOS devices. The present invention makes the interface traps density tests for gate oxide layers of n-type and p-type MOS devices completed on a same testing structure, this does not only shorten the measurement period by half but also decrease the costs for testing instruments, because the present testing method is based on a simple current-voltage scanning test without using equipments such as pulse generator required in conventional method. The testing results obtained according to the present invention are featured with spectral peak, which facilitates the data analysis and computation.

Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.

Abstract: The present invention discloses a radiation-hardened-by-design (RHBD) multi-gate device and a fabrication method thereof. The multi-gate device of the present invention includes a substrate; a source region and a drain region, which are on the substrate; a protruding fin structure and a field dielectric layer between the source region and the drain region on the substrate; a gate dielectric and a gate electrode on the fin structure and the dielectric layer; and two isolation layers separated to each other, which are disposed in the drain region between the adjacent two fins, wherein an interlayer is sandwiched between the two isolation layers.

Abstract: Congruent power and timing signals in a single electronic device. In an embodiment, a circuit may include just one isolation transformer operable to generate a power signal and a timing signal. On the secondary side, two branches may extract both a power signal and a clock signal for use in the circuit on the isolated secondary side. The first branch may be coupled to the transformer and operable to manipulate the signal into a power signal, such as a 5V DC signal. Likewise, the second circuit branch is operable to manipulate the signal into a clock signal, such as a 5 V signal with a frequency of 1 MHz. By extracting both a power supply signal and a clock signal from the same isolation transformer on the secondary side, valuable space may be saved on an integrated circuit device with only having a single winding for a single isolation transformer.

Abstract: A multi-granularity parallel storage system including a plurality of memories, a shift generator, an address increment lookup unit, an address shifter, a row address generator, and a plurality of address adders. The shift generator is configured to generate a shift value. The address increment lookup unit is configured to generate input data for the address shifter. The address shifter is configured to cyclically shift the input data rightward by Shift elements and then output the shifted data. The row address generator is configured to generate a row address RowAddr and input the generated row address RowAddr to the other input terminal of each address adder. Each address adder is configured to perform a non-sign addition of the input data at the two input terminals to obtain a read/write (R/W) address for one of the memories and input the R/W address to an address input terminal of the memory.

Abstract: A false-trigger free power-rail ESD clamp protection circuit includes an ESD impact detection component, a discharge transistor, a discharge transistor turn-on channel, and a discharge transistor shutoff channel. The circuit, in a smaller layout area, has very strong electrostatic charge discharge capability under ESD impact, little power leakage during normal power-up, and relatively strong false-trigger immunity capability for quick power-up.

Abstract: The present invention provides a thermal management system, an X-ray detection device and a CT apparatus. The thermal management system comprises a heater, an air mixing portion and a fan. The heater is provided at an air inlet of the air mixing portion. The air mixing portion provides an air mixing space for mixing exterior air that enters the air mixing portion with interior air of the air mixing portion. The fan is provided at an air outlet of the air mixing portion, and supplies the mixed air in the air mixing portion to a target object to be thermally managed. Therefore, a response time of the thermal management system to operate for an external temperature change may be lengthened, thus occurrence of abrupt change in a temperature of the target object as the external temperature changes abruptly may be avoided, improving a reliability of the thermal management system.

Abstract: Disclosed herein is a method for isolating active regions in a germanium-based MOS device. A surface of a germanium-based substrate is covered by a thin polysilicon layer or a poly-SiGe layer, and an isolation structure of germanium dioxide covered by a silicon dioxide layer or a SiGe oxide layer on top is formed by means of two steps of oxidation in a case of the active regions are protected. Such two steps of oxidation using the polysilicon layer or the poly-SiGe layer as a sacrificial layer is advantageous to improve the isolation quality of a fabricated germanium dioxide and to reduce a beak effect occurred during a local field oxygen oxidation so as to dramatically elevate the performance of the germanium device.

Abstract: The present disclosure provides a genetically-modified probiotic expressing recombinent phenylalanine ammonia Lyase (PAL) useful for treating phenylketonuria.

Abstract: A permanent magnet motor has a rotor and a stator. The rotor has a shaft, a rotor core and commutator fixed to the shaft, and rotor windings wound about poles of the rotor core and electrically connected to the commutator. The stator has an axially extending round housing, a ring magnet member fixed to an inner surface of the round housing, an endcap, and at least one pair of brushes in sliding contact with the commutator. A chamber is formed by the housing and the endcap. The commutator is disposed in the chamber. A window lift device incorporating the motor is also provided.

Abstract: Congruent power and timing signals in a single electronic device. In an embodiment, a circuit may include just one isolation transformer operable to generate a power signal and a timing signal. On the secondary side, two branches may extract both a power signal and a clock signal for use in the circuit on the isolated secondary side. The first branch may be coupled to the transformer and operable to manipulate the signal into a power signal, such as a 5V DC signal. Likewise, the second circuit branch is operable to manipulate the signal into a clock signal, such as a 5 V signal with a frequency of 1 MHz. By extracting both a power supply signal and a clock signal from the same isolation transformer on the secondary side, valuable space may be saved on an integrated circuit device with only having a single winding for a single isolation transformer.