Abstract: This application discloses an object detection method and a related device thereof. The method of this application includes: When object detection is to be performed on a target image, the target image including a to-be-detected object may be first obtained and then input to a target model. Next, the target model may perform feature extraction on the target image, to obtain a first feature of the target image. Then, the target model may encode the first feature of the target image, to obtain a second feature of the target image. Subsequently, the target model may decode the second feature of the target image based on a preset query vector, to obtain a third feature of the target image. Finally, the target model may obtain a detection result of the target image based on the third feature.

Abstract: An image processing method is disclosed in embodiments of this disclosure and is applied to the field of artificial intelligence. The method includes: obtaining an input feature map of an image to be processed, where the input feature map includes a first input sub-feature map and a second input sub-feature map, and resolution of the first input sub-feature map is higher than resolution of the second input sub-feature map; performing feature fusion processing on the input feature map by using a target network, to obtain an output feature map, where a feature of the first input sub-feature map is fused to a feature of the second input sub-feature map from a low level to a high level in the target network; and performing, based on the output feature map, object detection on the image to be processed, to obtain an object detection result.

Abstract: A vehicle window glass and a vehicle is provided. The vehicle window glass includes a laminated glass and an information collection region. The laminated glass includes an outer glass pane, an intermediate layer, and an inner glass pane. The intermediate layer is sandwiched between the outer glass pane and the inner glass pane. The outer glass pane has a first surface and a second surface opposite to the first surface, and the second surface faces the intermediate layer. The inner glass pane has a third surface and a fourth surface opposite to the second surface, and the third surface faces the intermediate layer. An anti-reflection film is disposed on the fourth surface of the inner glass pane, and in a thickness direction of the laminated glass, a projection of the anti-reflection film on the information collection region covers the information collection region.

Abstract: A data processing method includes obtaining input data, where the input image is image data or audio data; obtaining a second modal feature based on a first modal feature of the input data, where the first modal feature is a visual feature of the image data or an audio feature of the audio data, and the second modal feature is a character feature; and fusing the first modal feature and the second modal feature to obtain a target feature.

Abstract: This application provides a binary quantization method, a neural network training method, a device, and a storage medium. The binary quantization method includes: determining to-be-quantized data in a neural network; determining a quantization parameter corresponding to the to-be-quantized data, where the quantization parameter includes a scaling factor and an offset; determining, based on the scaling factor and the offset, a binary upper limit and a binary lower limit corresponding to the to-be-quantized data; and performing binary quantization on the to-be-quantized data based on the scaling factor and the offset, to quantize the to-be-quantized data into the binary upper limit or the binary lower limit.

Abstract: Embodiments of this application disclose a data processing method. The method is used in a multimodal fusion scenario, and the method includes obtaining first data and second data, where modalities of the first data and the second data are different. The method also includes obtaining a first feature set of the first data and a second feature set of the second data, and replacing a first target feature in the first feature set with a second target feature in the second feature set, to obtain a third feature set, where the second target feature corresponds to the first target feature. The method further includes obtaining a data feature based on the third feature set and the second feature set, where the data feature is used to implement a computer vision task.

Abstract: A glass, a glass assembly, and a vehicle are provided. The glass includes SiO2, Al2O3, Na2O, CaO, MgO, K2O, BaO, ZnO, TiO2, Sb2Ox, and total iron expressed as Fe2O3 of less than 180 parts per million (ppm), where ZnO+TiO2+Fe2O3?Sb2Ox, and 10 Fe2O3+ZnO+TiO2?Sb2Ox.

Abstract: An image processing method is disclosed in embodiments of this disclosure and is applied to the field of artificial intelligence. The method includes: obtaining an input feature map of an image to be processed, where the input feature map includes a first input sub-feature map and a second input sub-feature map, and resolution of the first input sub-feature map is higher than resolution of the second input sub-feature map; performing feature fusion processing on the input feature map by using a target network, to obtain an output feature map, where a feature of the first input sub-feature map is fused to a feature of the second input sub-feature map from a low level to a high level in the target network; and performing, based on the output feature map, object detection on the image to be processed, to obtain an object detection result.

Abstract: The technology of this application relates to a neural network distillation method, applied to the field of artificial intelligence, and includes processing to-be-processed data by using a first neural network and a second neural network to obtain a first target output and a second target output, where the first target output is obtained by performing kernel function-based transformation on an output of the first neural network layer, and the second target output is obtained by performing kernel function-based transformation on an output of the second neural network layer. The method further includes performing knowledge distillation on the first neural network based on a target loss constructed by using the first target output and the second target output.

Abstract: Design for testability (DFT) algorithms, which use both gradient descent and linear programming (LP) algorithms to insert test points (TPs) and/or scanned flip-flops (SFFs) into large circuits to make them testable are described. Scanning of either all flip-flops or a subset of flip-flops is supported. The algorithms measure testability using probabilities computed from logic simulation, Shannon's entropy measure (from information theory), and spectral analysis of the circuit in the frequency domain. The DFT hardware inserter methods uses toggling rates of the flip-flops (analyzed using digital signal processing (DSP) methods) and Shannon entropy measures of flip-flops to select flip-flops for scan. The optimal insertion of the DFT hardware reduces the amount of DFT hardware, since the gradient descent and linear program optimizations trade off inserting a TP versus inserting an SFF.

Abstract: Design for testability (DFT) algorithms, which use both gradient descent and linear programming (LP) algorithms to insert test points (TPs) and/or scanned flip-flops (SFFs) into large circuits to make them testable are described. Scanning of either all flip-flops or a subset of flip-flops is supported. The algorithms measure testability using probabilities computed from logic simulation, Shannon's entropy measure (from information theory), and spectral analysis of the circuit in the frequency domain. The DFT hardware inserter methods uses toggling rates of the flip-flops (analyzed using digital signal processing (DSP) methods) and Shannon entropy measures of flip-flops to select flip-flops for scan. The optimal insertion of the DFT hardware reduces the amount of DFT hardware, since the gradient descent and linear program optimizations trade off inserting a TP versus inserting an SFF.

Abstract: A scan-load-based (SLB) dynamic scan configuration reconfigures scan structures via scan-load operation, thereby eliminating interconnect network distributing configuration signals, and employs common scan circuitry identical for designs at mask level and is suitable for ASIC implementations. The architecture includes reconfigurable scan cells, apparatus for distributing configuration data to the reconfigurable scan cells and for determining desired reconfiguration data for each of the reconfigurable scan cells, and a configuration-set (CS) signal. Each of the reconfigurable scan cells has a pass-through (PT) mode in which data input, either a scan-in (SI) or a system-data (SD) of the scan cell, is transparently passed to a scan-out (SO) terminal of the scan cell without requiring a pulse on a shift clock (SC). The configuration-set (CS) signal communicates with each of the reconfigurable scan cells.

Abstract: A scan-load-based (SLB) dynamic scan configuration reconfigures scan structures via scan-load operation, thereby eliminating interconnect network distributing configuration signals, and employs common scan circuitry identical for designs at mask level and is suitable for ASIC implementations. The architecture includes reconfigurable scan cells, apparatus for distributing configuration data to the reconfigurable scan cells and for determining desired reconfiguration data for each of the reconfigurable scan cells, and a configuration-set (CS) signal. Each of the reconfigurable scan cells has a pass-through (PT) mode in which data input, either a scan-in (SI) or a system-data (SD) of the scan cell, is transparently passed to a scan-out (SO) terminal of the scan cell without requiring a pulse on a shift clock (SC). The configuration-set (CS) signal communicates with each of the reconfigurable scan cells.

Abstract: An architecture and method for improving efficiency of a Class-A power amplifier by dynamically scaling biasing current thereof as well as synchronously compensating gain thereof in order to maintain overall constant gain of the Class-A power amplifier at all biasing configurations thereof. A biasing-current switching-network is operatively connected to the back-end block of the Class-A power amplifier. A gain-control switching-network is operatively connected to a front-end block of the Class-A power amplifier. A detector-and-control block is operatively connected to an output of the back-end block of the Class-A power amplifier, and samples a signal that is then compared with reference signals to determine switching configurations in the biasing-current switching-network and the gain-control switching network when the signal is processed through the front-end block of the Class-A power amplifier followed by the back-end block of the Class-A power amplifier.

Abstract: An architecture and method for improving efficiency of a Class-A power amplifier by dynamically scaling biasing current thereof as well as synchronously compensating gain thereof in order to maintain overall constant gain of the Class-A power amplifier at all biasing configurations thereof. A biasing-current switching-network is operatively connected to the back-end block of the Class-A power amplifier. A gain-control switching-network is operatively connected to a front-end block of the Class-A power amplifier. A detector-and-control block is operatively connected to an output of the back-end block of the Class-A power amplifier, and samples a signal that is then compared with reference signals to determine switching configurations in the biasing-current switching-network and the gain-control switching network when the signal is processed through the front-end block of the Class-A power amplifier followed by the back-end block of the Class-A power amplifier.

Abstract: A method for improving the efficiency of test sequences for circuits with embedded multiple-port arrays, such as random access memory (RAM), is described, With existing test generation methods, it is a common occurrence that a resulting test sequence only utilizes a minimum number of read ports for detecting a target fault. When this type of test sequences is applied, one or more outputs of embedded RAMs may not attain known values, consequently reducing the effectiveness of the test sequences. The present invention enhances test sequences to that when they are applied, all outputs of embedded RAMs attain known values.

Abstract: A method for improving the efficiency of test sequences for circuits with embedded multiple-port arrays, such as random access memory (RAM), is described, With existing test generation methods, it is a common occurrence that a resulting test sequence only utilizes a minimum number of read ports for detecting a target fault. When this type of test sequences is applied, one or more outputs of embedded RAMs may not attain known values, consequently reducing the effectiveness of the test sequences. The present invention enhances test sequences to that when they are applied, all outputs of embedded RAMs attain known values.

Abstract: A method for improving the efficiency of test sequences for circuits with embedded multiple-port arrays, such as random access memory (RAM), is described. With existing test generation methods, it is a common occurrence that a resulting test sequence only utilizes a minimum number of read ports for detecting a target fault. When this type of test sequences is applied, one or more outputs of embedded RAMs may not attain known values, consequently reducing the effectiveness of the test sequences. The present invention enhances test sequences so that when they are applied, all outputs of embedded RAMs attain known values.

Abstract: A method for improving the efficiency of fault simulation using logic fault backtracing is described. With existing fault tracing methods, it is a common occurrence that too many faults are identified as potential faults to be processed by fault simulation. The method of the invention improves the fault-simulation efficiency by explicitly processing only those faults that are identified by logic fault tracing as potential faults. The present invention also reduces the storage usage with concurrent fault simulations.