Abstract: A driving circuit and a display device are provided. The driving circuit includes a pull-up node, an input module, a pull-up module, a first output module and a second output module; the input module is electrically connected to an input terminal and a pull-up node, and is configured to control a potential of the pull-up node under the control of an input signal provided by the input terminal; the pull-up module controls the potential of the pull-up node; the first output module outputs a first gate driving signal through the first driving output terminal under the control of the potential of the pull-up node; the second output module outputs a second gate driving signal through the second driving output terminal under the control of the potential of the pull-up node. The present disclosure may output a plurality of stages of gate driving signals and reduce the number of transistors, which is facilitate to the narrow border.

Abstract: A display substrate and a display apparatus provided by the present disclosure include a plurality of pixels arranged in an array, where each of the pixels includes a plurality of sub-pixels, each of the sub-pixels includes a first domain area and a second domain area, and the first domain area and the second domain area each has at least two orientations; a plurality of data lines, where each of the data lines is electrically connected with first domain areas and second domain areas of a same column of sub-pixels; and a plurality of discharge wires, where each of the discharge wires is electrically connected with the second domain areas of the same column of the sub-pixels, and the discharge wires are configured for providing at least two direct current signals to two adjacent columns of pixels.

Abstract: A driving circuit and a display device are provided. The driving circuit includes a pull-up node, an input module, a pull-up module, a first output module and a second output module; the input module is electrically connected to an input terminal and a pull-up node, and is configured to control a potential of the pull-up node under the control of an input signal provided by the input terminal; the pull-up module controls the potential of the pull-up node; the first output module outputs a first gate driving signal through the first driving output terminal under the control of the potential of the pull-up node; the second output module outputs a second gate driving signal through the second driving output terminal under the control of the potential of the pull-up node. The present disclosure may output a plurality of stages of gate driving signals and reduce the number of transistors, which is facilitate to the narrow border.

Abstract: A liquid crystal display panel and a preparation method therefor are provided, including: an array substrate and a color filter substrate arranged opposite; the array substrate and the color filter substrate are correspondingly provided with a pixel region, during display the pixel region has an alignment dark fringe caused by photo-alignment, and the alignment dark fringe includes a dark fringe branch line located at an edge of the pixel region, wherein the color filter substrate is provided with a common electrode and a black matrix configured to define the pixel region, the array substrate is provided with a main pixel electrode and an edge voltage source, the edge voltage source is located at an edge of the pixel region and below the black matrix.

Abstract: A liquid crystal display panel and a preparation method therefor are provided, including: an array substrate and a color filter substrate arranged opposite; the array substrate and the color filter substrate are correspondingly provided with a pixel region, during display the pixel region has an alignment dark fringe caused by photo-alignment, and the alignment dark fringe includes a dark fringe branch line located at an edge of the pixel region, wherein the color filter substrate is provided with a common electrode and a black matrix configured to define the pixel region, the array substrate is provided with a main pixel electrode and an edge voltage source, the edge voltage source is located at an edge of the pixel region and below the black matrix.