Patents by Inventor Xingxing CHEN

Xingxing CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136312
    Abstract: A semiconductor device includes a first wafer having a deep trench capacitor and a second wafer bonded to the first wafer, in which the second wafer includes a first active device on a first silicon-on-insulator (SOI) substrate and a first metal interconnection connected to the first active device and the deep trench capacitor. The first wafer further includes the deep trench capacitor disposed in a substrate, a first inter-layer dielectric (ILD) layer on the deep trench capacitor, a first inter-metal dielectric (IMD) layer on the first ILD layer, and a second metal interconnection in the first ILD layer and the first IMD layer.
    Type: Application
    Filed: November 17, 2022
    Publication date: April 25, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Ching-Yang Wen, XINGXING CHEN
  • Patent number: 11955292
    Abstract: A structure of capacitors connected in parallel includes a substrate. A trench embedded in the substrate. Numerous electrode layers respectively conformally fill in and cover the trench. The electrode layers are formed of numerous nth electrode layers, wherein n is a positive integer from 1 to M, and M is not less than 3. The nth electrode layer with smaller n is closer to the sidewall of the trench. When n equals to M, the Mth electrode layer fills in the center of the trench, and the top surface of the Mth electrode is aligned with the top surface of the substrate. A capacitor dielectric layer is disposed between the adjacent electrode layers. A first conductive plug contacts the nth electrode layer with odd-numbered n. A second conductive plug contacts the nth electrode layer with even-numbered n.
    Type: Grant
    Filed: November 15, 2022
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Ching-Yang Wen, Xingxing Chen, Chao Jin
  • Patent number: 11947248
    Abstract: A stop switch assembly includes a movable block, a pressing portion, a driving rod, a driving pin and an elastic member. The movable block includes a first pair and a second pair of opposite side surfaces, a hole is defined in the movable block passing through the first pair of side surfaces and an inclined slot is defined in the movable block passing through the second pair of side surfaces. The driving pin is inserted in the driving rod with its head movably arranged in the inclined slot. The elastic member is arranged between the pressing portion and the movable block for applying an elastic bias to the pressing portion to allow the pressing portion being away from the movable block. When the pressing part is pressed, the driving pin slides in the inclined slot and drives the movable block moving between a first position and a second position.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: April 2, 2024
    Assignee: SHENZHEN LEQI NETWORK TECHNOLOGY CO., LTD.
    Inventors: Paihan Chen, Xingxing Yuan
  • Publication number: 20240088354
    Abstract: A battery electrode includes a first metal foil, a second metal foil, and a thermoplastic polymer layer between the first metal foil and the second metal foil. The battery electrode also includes a first coating adjacent to the first metal foil such that the first metal foil is between the thermoplastic polymer layer and the first coating. The battery electrode also includes a second coating adjacent to the second metal foil such that the second metal foil is between the thermoplastic polymer layer and the second coating.
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Inventors: Xiaoyun Yang, Aaron Smith, Wanjie Zhang, Siva Ram Kumar Muthukumar, Kai Yu, Enbang Wang, Yafeng Chen, Rohit Bedida, Xiaoyu Shen, Xingxing Zhang
  • Patent number: 11929213
    Abstract: A structure of capacitors connected in parallel includes a substrate. A trench embedded in the substrate. Numerous electrode layers respectively conformally fill in and cover the trench. The electrode layers are formed of numerous nth electrode layers, wherein n is a positive integer from 1 to M, and M is not less than 3. The nth electrode layer with smaller n is closer to the sidewall of the trench. When n equals to M, the Mth electrode layer fills in the center of the trench, and the top surface of the Mth electrode is aligned with the top surface of the substrate. A capacitor dielectric layer is disposed between the adjacent electrode layers. A first conductive plug contacts the nth electrode layer with odd-numbered n. A second conductive plug contacts the nth electrode layer with even-numbered n.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: March 12, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Ching-Yang Wen, Xingxing Chen, Chao Jin
  • Publication number: 20230154926
    Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.
    Type: Application
    Filed: January 11, 2023
    Publication date: May 18, 2023
    Inventors: Sheng Zhang, Chunyuan QI, Xingxing Chen, Chien-Kee Pang
  • Publication number: 20230094739
    Abstract: An silicon-on-insulator substrate is provided in the present invention, including a handler, a polysilicon trap-rich layer formed on the handler, an oxide layer formed on the polysilicon trap-rich layer and a monocrystalline silicon layer formed directly on the oxide layer, wherein a bonding interface is between the monocrystalline silicon layer and the oxide layer.
    Type: Application
    Filed: October 26, 2021
    Publication date: March 30, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: CHUNYUAN QI, Sheng Zhang, XINGXING CHEN, Chien-Kee Pang
  • Patent number: 11605648
    Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: March 14, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Sheng Zhang, Chunyuan Qi, Xingxing Chen, Chien-Kee Pang
  • Publication number: 20230071686
    Abstract: A structure of capacitors connected in parallel includes a substrate. A trench embedded in the substrate. Numerous electrode layers respectively conformally fill in and cover the trench. The electrode layers are formed of numerous nth electrode layers, wherein n is a positive integer from 1 to M, and M is not less than 3. The nth electrode layer with smaller n is closer to the sidewall of the trench. When n equals to M, the Mth electrode layer fills in the center of the trench, and the top surface of the Mth electrode is aligned with the top surface of the substrate. A capacitor dielectric layer is disposed between the adjacent electrode layers. A first conductive plug contacts the nth electrode layer with odd-numbered n. A second conductive plug contacts the nth electrode layer with even-numbered n.
    Type: Application
    Filed: November 15, 2022
    Publication date: March 9, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Ching-Yang Wen, XINGXING CHEN, CHAO JIN
  • Publication number: 20220415926
    Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.
    Type: Application
    Filed: July 22, 2021
    Publication date: December 29, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Sheng Zhang, Chunyuan Qi, Xingxing Chen, Chien-Kee Pang
  • Patent number: 11398548
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: July 26, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Shen Li, Ching-Yang Wen, Purakh Raj Verma, Xingxing Chen, Chee-Hau Ng
  • Publication number: 20210313116
    Abstract: A structure of capacitors connected in parallel includes a substrate. A trench embedded in the substrate. Numerous electrode layers respectively conformally fill in and cover the trench. The electrode layers are formed of numerous nth electrode layers, wherein n is a positive integer from 1 to M, and M is not less than 3. The nth electrode layer with smaller n is closer to the sidewall of the trench. When n equals to M, the Mth electrode layer fills in the center of the trench, and the top surface of the Mth electrode is aligned with the top surface of the substrate. A capacitor dielectric layer is disposed between the adjacent electrode layers. A first conductive plug contacts the nth electrode layer with odd-numbered n. A second conductive plug contacts the nth electrode layer with even-numbered n.
    Type: Application
    Filed: April 21, 2020
    Publication date: October 7, 2021
    Inventors: Purakh Raj Verma, Ching-Yang Wen, XINGXING CHEN, CHAO JIN
  • Publication number: 20210104602
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.
    Type: Application
    Filed: December 16, 2020
    Publication date: April 8, 2021
    Applicant: United Microelectronics Corp.
    Inventors: Wen-Shen Li, Ching-Yang Wen, Purakh Raj Verma, Xingxing Chen, Chee-Hau Ng
  • Publication number: 20210063322
    Abstract: A grain mildew detection method and device based on a WiFi apparatus. The method includes the following steps: acquiring a WiFi signal which passes through a grain region, extracting channel state information (CSI) amplitude data from the WiFi signal, and acquiring grain statuses corresponding to the CSI amplitude data; establishing a neural network model, and training the neural network model by using the acquired CSI amplitude data and the grain statuses corresponding to the CSI amplitude data, to obtain an amplitude-status relationship model; and acquiring a WiFi signal which passes through a region in which grain to be detected is located, extracting CSI amplitude data from the WiFi signal which passes through the region in which the grain to be detected is located, and inputting the CSI amplitude data into the amplitude-status relationship model, to obtain a grain status of the grain to be detected.
    Type: Application
    Filed: September 2, 2020
    Publication date: March 4, 2021
    Inventors: Weidong Yang, Pengming Hu, Yuan Zhang, Wei Wei, Zhi Li, Yao Qin, Chunhua Zhu, Yuying Jiang, Wenshuai Zhang, Xingxing Chen
  • Patent number: 10903314
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: January 26, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Shen Li, Ching-Yang Wen, Purakh Raj Verma, Xingxing Chen, Chee-Hau Ng
  • Patent number: 10518396
    Abstract: A drive blade lubrication assembly for use in a powered fastener driver (10). The powered fastener driver (10) contains a drive blade (42) which snap-fits with a reciprocating piston (58) by a blade seal (103) assembly. The drive blade lubrication assembly contains a lubricant applying member adapted to apply lubricant to a portion of the drive blade (42); and a lubricant storing device which is in fluid communication with the lubricant applying member. The lubricating storing device is adapted to replenish the lubricant in the lubricant applying member. A powered fastener driver (10) containing a drive blade lubrication assembly is also described. The use of the lubricant storing device in the present invention ensures that lubricant is continuously supplied to the drive blade (42) after long time usage of the powered fastener driver (10), so that friction between the drive blade and the blade seal assembly is minimized.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: December 31, 2019
    Assignee: TTI (MACAO COMMERCIAL OFFSHORE) LIMITED
    Inventors: Xingxing Chen, Jingfeng Zhou, Liguo Ma, Jinlin Zhou
  • Publication number: 20190355812
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.
    Type: Application
    Filed: June 25, 2018
    Publication date: November 21, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Wen-Shen Li, Ching-Yang Wen, Purakh Raj Verma, Xingxing Chen, Chee-Hau Ng
  • Publication number: 20190051666
    Abstract: A semiconductor device includes a substrate having a frontside and a backside. The substrate includes a semiconductor layer and a buried insulator layer. A transistor is disposed on the semiconductor layer. An interlayer dielectric (ILD) layer is disposed on the frontside and covering the transistor. A contact structure penetrates through the ILD layer, the semiconductor layer and the buried insulator layer. A silicide layer caps an end surface of the contact structure on the backside. A passive element is disposed on the backside of the substrate. The contact structure is electrically connected to the passive element.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 14, 2019
    Inventors: Wen-Shen Li, XIAOYUAN ZHI, XINGXING CHEN, Ching-Yang Wen
  • Publication number: 20170326715
    Abstract: A drive blade lubrication assembly for use in a powered fastener driver (10). The powered fastener driver (10) contains a drive blade (42) which snap-fits with a reciprocating piston (58) by a blade seal (103) assembly. The drive blade lubrication assembly contains a lubricant applying member adapted to apply lubricant to a portion of the drive blade (42); and a lubricant storing device which is in fluid communication with the lubricant applying member. The lubricating storing device is adapted to replenish the lubricant in the lubricant applying member. A powered fastener driver (10) containing a drive blade lubrication assembly is also described.
    Type: Application
    Filed: December 23, 2014
    Publication date: November 16, 2017
    Inventors: Xingxing CHEN, Jingfeng ZHOU, Liguo MA, Jinlin ZHOU