Abstract: A path planning method and a biped robot using the same are provided. The method includes: generating a candidate node set for a next foot placement based on a biped robot's own parameters and joint information of a current node, adding valid candidate nodes in the candidate node set to a priority queue so as to select optimal nodes for realizing next node expansion. These optimal nodes are output to generate a foot placement sequence from an initial node to a target node, which can greatly reduce the search amount for path nodes when the robot's legs intersect and touch the ground, thereby improving the efficiency of path planning.

Abstract: This application relates to a heating assembly, a battery, and an electrical device. A heating sheet is affixed to a surface of a battery cell to heat the battery cell. When the battery cell thermally expands, cracks can break under an expansion force of the battery cell, so that the heating sheet deforms synchronously with the battery cell to prevent the heating sheet from being detached from the battery cell, thereby improving the efficiency of the heating sheet in heating the battery cell.

Abstract: A robot balance control method as well as a robot using the same and a computer readable storage medium are provided. In the method, a brand new flywheel model different from the existing flywheel model is created. In this flywheel model, the foot of the support leg of the robot is equivalent to the massless link of the flywheel model, while rest parts of the robot are equivalent to the flywheel of the flywheel model. Compared with the various models in the prior art, this flywheel model is more in line with the actual situation of the robot during the monoped supporting period. By controlling the posture of the foot of the support leg based on this flywheel model, a better balance effect can be achieved, which avoids the overturning of the robot.

Abstract: A drug conjugate, such as an antibody drug conjugate, and the use thereof, belonging to the field of biomedicine. In some embodiments, the drug conjugate is a compound of Formula I or a pharmaceutically acceptable salt or a solvate thereof, and can be used for treating cancers, autoimmune diseases, inflammatory diseases or infectious diseases.

Abstract: A metasurface structure includes a substrate having a first region and a second region not overlapping with the first region; a first pillar element within the first region on the substrate; and a second pillar element within the second region on the substrate. The first pillar element has a first sectional profile and the second pillar element has a second sectional profile that is different from the first sectional profile. At least one of the first sectional profile and the second sectional profile is of a non-rectangular shape.

Abstract: The present invention provides a dynamic joint distribution alignment network-based bearing fault diagnosis method under variable working conditions, including acquiring bearing vibration data under different working conditions to obtain a source domain sample and a target domain sample; establishing a deep convolutional neural network model with dynamic joint distribution alignment; feeding both the source domain sample and the target domain sample into the deep convolutional neural network model with initialized parameters, and extracting, by a feature extractor, high-level features of the source domain sample and the target domain sample; calculating a marginal distribution distance and a conditional distribution distance; obtaining a joint distribution distance according to the marginal distribution distance and the conditional distribution distance, and combining the joint distribution distance and a label loss to obtain a target function; and optimizing the target function by using SGD, and training the

Abstract: A semiconductor device includes a first wafer having a deep trench capacitor and a second wafer bonded to the first wafer, in which the second wafer includes a first active device on a first silicon-on-insulator (SOI) substrate and a first metal interconnection connected to the first active device and the deep trench capacitor. The first wafer further includes the deep trench capacitor disposed in a substrate, a first inter-layer dielectric (ILD) layer on the deep trench capacitor, a first inter-metal dielectric (IMD) layer on the first ILD layer, and a second metal interconnection in the first ILD layer and the first IMD layer.

Abstract: A heart rate detection module and an electronic device are disclosed. The heart rate detection module includes a substrate, and a light source, an optical receiver, a light blocking portion, and an optical film that are disposed on the substrate. The light blocking portion is disposed between the light source and the optical receiver, so that the light source is optically isolated from the optical receiver. The optical film covers the light source, the light blocking portion, and the optical receiver, and a light filtering portion is disposed on a side that is of the optical film and that faces the substrate.

Abstract: A method for determining antenna rule for a radio-frequency (RF) device includes the steps of forming a gate structure on a substrate, forming a source/drain region adjacent to the gate structure, forming a first metal routing on the source/drain region, and then forming a second metal routing on the gate structure. Preferably, a sum of an area of the first metal routing and an area of the second metal routing divided by an area of the gate structure is less than a ratio.

Abstract: A semiconductor device includes a first wafer having a deep trench capacitor and a second wafer bonded to the first wafer, in which the second wafer includes a first active device on a first silicon-on-insulator (SOI) substrate and a first metal interconnection connected to the first active device and the deep trench capacitor. The first wafer further includes the deep trench capacitor disposed in a substrate, a first inter-layer dielectric (ILD) layer on the deep trench capacitor, a first inter-metal dielectric (IMD) layer on the first ILD layer, and a second metal interconnection in the first ILD layer and the first IMD layer.

Abstract: A structure of capacitors connected in parallel includes a substrate. A trench embedded in the substrate. Numerous electrode layers respectively conformally fill in and cover the trench. The electrode layers are formed of numerous nth electrode layers, wherein n is a positive integer from 1 to M, and M is not less than 3. The nth electrode layer with smaller n is closer to the sidewall of the trench. When n equals to M, the Mth electrode layer fills in the center of the trench, and the top surface of the Mth electrode is aligned with the top surface of the substrate. A capacitor dielectric layer is disposed between the adjacent electrode layers. A first conductive plug contacts the nth electrode layer with odd-numbered n. A second conductive plug contacts the nth electrode layer with even-numbered n.

Abstract: A structure of capacitors connected in parallel includes a substrate. A trench embedded in the substrate. Numerous electrode layers respectively conformally fill in and cover the trench. The electrode layers are formed of numerous nth electrode layers, wherein n is a positive integer from 1 to M, and M is not less than 3. The nth electrode layer with smaller n is closer to the sidewall of the trench. When n equals to M, the Mth electrode layer fills in the center of the trench, and the top surface of the Mth electrode is aligned with the top surface of the substrate. A capacitor dielectric layer is disposed between the adjacent electrode layers. A first conductive plug contacts the nth electrode layer with odd-numbered n. A second conductive plug contacts the nth electrode layer with even-numbered n.

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.

Abstract: An silicon-on-insulator substrate is provided in the present invention, including a handler, a polysilicon trap-rich layer formed on the handler, an oxide layer formed on the polysilicon trap-rich layer and a monocrystalline silicon layer formed directly on the oxide layer, wherein a bonding interface is between the monocrystalline silicon layer and the oxide layer.

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.

Abstract: A structure of capacitors connected in parallel includes a substrate. A trench embedded in the substrate. Numerous electrode layers respectively conformally fill in and cover the trench. The electrode layers are formed of numerous nth electrode layers, wherein n is a positive integer from 1 to M, and M is not less than 3. The nth electrode layer with smaller n is closer to the sidewall of the trench. When n equals to M, the Mth electrode layer fills in the center of the trench, and the top surface of the Mth electrode is aligned with the top surface of the substrate. A capacitor dielectric layer is disposed between the adjacent electrode layers. A first conductive plug contacts the nth electrode layer with odd-numbered n. A second conductive plug contacts the nth electrode layer with even-numbered n.

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.

Abstract: A structure of capacitors connected in parallel includes a substrate. A trench embedded in the substrate. Numerous electrode layers respectively conformally fill in and cover the trench. The electrode layers are formed of numerous nth electrode layers, wherein n is a positive integer from 1 to M, and M is not less than 3. The nth electrode layer with smaller n is closer to the sidewall of the trench. When n equals to M, the Mth electrode layer fills in the center of the trench, and the top surface of the Mth electrode is aligned with the top surface of the substrate. A capacitor dielectric layer is disposed between the adjacent electrode layers. A first conductive plug contacts the nth electrode layer with odd-numbered n. A second conductive plug contacts the nth electrode layer with even-numbered n.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.