Abstract: The present disclosure discloses a semiconductor device, a method of manufacturing the same, and a semiconductor package structure. The semiconductor device including a substrate, a multilayer semiconductor layer located on one side of the substrate, in which a Two-Dimensional Electron Gas is formed, a first source, a first gate and a first drain located on one side of the multilayer semiconductor layer and located within an active region of the multilayer semiconductor layer, the first gate being located between the first source and the first drain, and a back surface gate contact electrode located on one side of the substrate away from the multilayer semiconductor layer, wherein the first gate is electrically connected to the back surface gate contact electrode. A signal is provided from the back surface of the semiconductor device to the first gate, to reduce the parasitic inductance and parasitic resistance caused by the device during the packaging process.

Abstract: Disclosed are a semiconductor device and a preparation method thereof. The semiconductor device includes a substrate; a multilayer semiconductor layer located on a side of the substrate; and a source, a gate, a drain and a field plate structure located on a side, away from the substrate, of the multilayer semiconductor layer. The field plate structure includes a main body portion and a first extension portion; the main body portion is located between the gate and the drain; the first extension portion is connected to the main body portion and is located on a side, away from the multilayer semiconductor layer, of the gate; and the first extension portion at least partially overlaps the gate. By adopting the above technical solution, the probability of the breakdown, which occurs at the side of the gate near the drain, may be reduced, thereby increasing the reliability of semiconductor devices.

Abstract: The present disclosure discloses a semiconductor device, a method of manufacturing the same, and a semiconductor package structure. The semiconductor device including a substrate, a multilayer semiconductor layer located on one side of the substrate, in which a Two-Dimensional Electron Gas is formed, a first source, a first gate and a first drain located on one side of the multilayer semiconductor layer and located within an active region of the multilayer semiconductor layer, the first gate being located between the first source and the first drain, and a back surface gate contact electrode located on one side of the substrate away from the multilayer semiconductor layer, wherein the first gate is electrically connected to the back surface gate contact electrode. A signal is provided from the back surface of the semiconductor device to the first gate, to reduce the parasitic inductance and parasitic resistance caused by the device during the packaging process.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same, and it relates to a field of semiconductor technology. The semiconductor device includes a substrate, a semiconductor layer, a dielectric layer, a source, a drain, and a gate, wherein a first face of the gate close to a side of the drain and close to the semiconductor layer has a first curved face. A gate trench corresponding to the gate is provided on the dielectric layer, a material of the gate being filled in the gate trench, and at least a part of a second face of the gate trench in contact with the gate is a second curved face which extends from a surface of the dielectric layer away from the semiconductor layer toward the semiconductor layer.

Abstract: In implementations of the subject matter described herein, a device is provided. The device comprises a power source and a display. The device also comprises a buffer in communication with the display. The buffer is configured to store information to be displayed on the display. The device further comprises a power management unit. In a power-off mode of the device where remaining capacity of the power source is below a threshold, the power management unit powers the display and the buffer, so that the display can display the information stored in the buffer. In this way, even if the device is in the power-off mode due to the low capacity of the power source, the display can still present useful information to the user.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same, and it relates to a field of semiconductor technology. The semiconductor device includes a substrate, a semiconductor layer, a dielectric layer, a source, a drain, and a gate, wherein a first face of the gate close to a side of the drain and close to the semiconductor layer has a first curved face. A gate trench corresponding to the gate is provided on the dielectric layer, a material of the gate being filled in the gate trench, and at least a part of a second face of the gate trench in contact with the gate is a second curved face which extends from a surface of the dielectric layer away from the semiconductor layer toward the semiconductor layer.

Abstract: Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same. The semiconductor device includes an active region and an inactive region located outside of the active region, the semiconductor device including a substrate, a semiconductor layer including a first semiconductor layer located in the active region and a second semiconductor layer located in the inactive region, a source, a drain, and a gate. A via hole penetrated through the substrate and the semiconductor layers below the source is provided below the source. A part of the via hole is located in the second semiconductor layer of the inactive region and penetrates at least one part of the second semiconductor layer.

Abstract: Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same. The semiconductor device includes an active region and an inactive region located outside of the active region, the semiconductor device including a substrate, a semiconductor layer including a first semiconductor layer located in the active region and a second semiconductor layer located in the inactive region, a source, a drain, and a gate. A via hole penetrated through the substrate and the semiconductor layers below the source is provided below the source. A part of the via hole is located in the second semiconductor layer of the inactive region and penetrates at least one part of the second semiconductor layer.

Abstract: In implementations of the subject matter described herein, a device is provided. The device comprises a power source and a display. The device also comprises a buffer in communication with the display. The buffer is configured to store information to be displayed on the display. The device further comprises a power management unit. In a power-off mode of the device where remaining capacity of the power source is below a threshold, the power management unit powers the display and the buffer, so that the display can display the information stored in the buffer. In this way, even if the device is in the power-off mode due to the low capacity of the power source, the display can still present useful information to the user.