Abstract: Disclosed are an isolation method for a high-performance computer system, and a high-performance computer system. The isolation method comprises node-level isolation performed. The node-level isolation comprises: configuring a routing table for each computing node, and configuring, in the routing table, valid routing information for computing node pairs; when any one source computing node needs to communicate with a target computing node, determining, by lookup, whether valid routing information exists between the source computing node and the target computing node according to the configured routing table; if so, allowing the source computing node to communicate with the target computing node; otherwise, forbidding the source computing node from communicating with the target computing node.

Abstract: The present application provides an interposer, including an interposer substrate, at least one through silicon via, a first shield layer, a first insulation layer, a first cable layout layer, and at least one first bump. The interposer substrate includes an upper surface and a lower surface; the at least one through silicon via is buried in the interposer substrate and runs through the upper surface and the lower surface; the first shield layer is disposed on the upper surface of the interposer substrate and the first shield layer has electrical conductivity; the first insulation layer is disposed at the first shield layer; the first cable layout layer is disposed at the first insulation layer and is electrically connected to the at least one through silicon via.

Abstract: The present application provides an interposer, including an interposer substrate, at least one through silicon via, a first shield layer, a first insulation layer, a first cable layout layer, and at least one first bump. The interposer substrate includes an upper surface and a lower surface; the at least one through silicon via is buried in the interposer substrate and runs through the upper surface and the lower surface; the first shield layer is disposed on the upper surface of the interposer substrate and the first shield layer has electrical conductivity; the first insulation layer is disposed at the first shield layer; the first cable layout layer is disposed at the first insulation layer and is electrically connected to the at least one through silicon via.