Abstract: A metal-organic framework material separation membrane and a preparation method for the metal-organic framework material separation membrane are provided. The metal-organic framework material separation membrane has a base membrane and a metal-organic framework material functional layer. The metal-organic framework material functional layer comprises has an inter-embedded polyhedron structure. The preparation metal-organic framework material separation membrane includes the steps of: (1) preparing a solution containing a first organic solvent, an organic ligand, a metal compound, and an auxiliary agent; (2) subjecting a base membrane to a pretreatment, involving introducing, on the surface of the base membrane, metal atoms from the metal compound of step (1); and (3) mixing the pretreated base membrane of step (2) with the solution of step (1) to obtain a first mixture, and then heating the first mixture for reaction, so as to prepare a metal-organic framework material separation membrane.

Abstract: Provided in the present application are an amide compound, and an isomer, a pharmaceutically acceptable salt, and a pharmaceutical composition thereof, and the use thereof. The amide compound has a structure as represented by formula I. The amide compound of the present application has a significant JAK kinase inhibitory activity, especially a JAKI kinase inhibitory activity, has a higher inhibitory activity on JAK1 kinase than on JAK2 kinase, and can be used as a highly selective JAK1 kinase inhibitor. Therefore, the amide compound of the present application can be used for preparing drugs for treating JAK1 kinase-mediated diseases.

Abstract: Disclosed are systems and methods for providing multi-phased programming with balanced Gray coding. A method includes programming, in a first phase, a first portion of data into memory cells of a flash memory in a first-level cell mode. The method also includes retaining, in a cache, at least a subset of the data. The method also includes regenerating the data from at least the cache, wherein the regenerated data includes a second portion of the data. The method also includes programming, in a second phase, the regenerated data in a second-level cell mode based on a mapping from the first-level cell mode to the second-level cell mode. The mapping maps each state distribution in the first-level cell mode to at least two non-adjacent state distributions in the second-level cell mode, and a width of each state distribution in the first-level cell mode may be narrowed.

Abstract: A method includes receiving a first polynomial and a second polynomial, both of order n?1 and forming d polynomial segments from both the first polynomial and the second polynomial such that each polynomial segment is of order (n/d)?1. The polynomial segments of the first polynomial and the d polynomial segments of the second polynomial are used to form segment products. Each segment product is divided into a first polynomial substructure of order n/d and a second polynomial substructure of order (n/d)?1. A first polynomial substructure containing the first n/d coefficients of a product of the first polynomial and the second polynomial is summed with a second polynomial substructure to form a sum substructure. The sum substructure is used multiple times to determine coefficients of a polynomial representing the modulo xn+1 of the product of the first polynomial and the second polynomial.

Abstract: A modular polynomial multiplier includes a plurality of processing elements. Each includes a multiplication unit, an addition unit and a delay unit. The addition unit has an input connected to the output of the multiplication unit. The delay unit is connected to the output of the addition unit delays values by one clock cycle. The first input of the multiplication unit of each processing element carries a respective coefficient of a first polynomial and the second input of the multiplication unit of each processing element is connected to one of an input line carrying a sequence of coefficients of a second polynomial having n coefficients and a delay line carrying the sequence of coefficients of the second polynomial delayed by n clock cycles and negated.

Abstract: A high salinity wastewater treatment system is provided according to the present application, which includes a hydrogel loading system and a flow-storage different-oriented-inlet-and-outlet system. The hydrogel loading system includes six separation plates, a wastewater treatment area, a water distribution bin, a rotating shaft, a driving motor and a fixed bracket. The six separation plates evenly separate the wastewater treatment area into six separate treatment sectors in an axial direction. The six separate treatment sectors are filled with hydrogel materials with water purification effect. The high salinity wastewater infiltrates into each separate treatment sector one by one through high salinity wastewater inlet meshes on a surface of the wastewater treatment area, and the purified high salinity wastewater is discharged through a wastewater cleaning outlet pipe with a same water inlet direction as a cleaning filler distribution pipe.

Abstract: An alternating cascaded system for high-salinity wastewater treatment includes a pollutant removal system and an alternating cascaded water conveyance system embedded in the pollutant removal system. The pollutant removal system includes four partition plates, a pollutant removal zone and a discharge sump; and the alternating cascaded water conveyance system includes feed water distribution channels disposed under a feed water conveyer pipe and on an outer wall of a first pollutant removal subzone, cleaning water distribution channels disposed on an outer wall of a third pollutant removal subzone and located under a cleaning water pipe, and a purified water discharge pipe and a cleaning water discharge pipe that are located in the discharge sump and axially have a same discharge direction from top to bottom.

Abstract: A movably-connected and continuously-connected apparatus for uninterrupted high-salinity wastewater purification includes a high-salinity wastewater adsorption treatment system and a movably-connected drainage system embedded in the treatment system. The high-salinity wastewater adsorption treatment system includes four purification zone partition plates, a hollow cylindrical purification zone, a cylindrical water distribution sump located in an axial center of the purification zone, a rotating shaft, a motor, a fixed support and a water tank; the four purification zone partition plates include a first partition plate forming an angle of 135° with a horizontal direction from left to right, a second partition plate forming an angle of 45° with the horizontal direction from left to right, a third partition plate forming an angle of 135° with a vertical direction from bottom to top and a fourth partition plate forming an angle of 135° with the vertical direction from bottom to top.

Abstract: The present disclosure discloses scutellarin amide derivatives and preparation methods and uses thereof, which belongs to the field of natural drugs and medicinal chemistry. The scutellarin amide derivatives according to the present disclosure and pharmaceutically acceptable salts thereof have a structure as shown in the following general formula I: scutellarin derivatives, which are prepared by amidation at the glycosylcarboxyl site, can be used in the manufacture of anti-tumor drugs, which have a good effect against tumor cell proliferation.

Abstract: Disclosed are systems and methods for providing multi-phased programming with balanced Gray coding. A method includes programming, in a first phase, a first portion of data into memory cells of a flash memory in a first-level cell mode. The method also includes retaining, in a cache, at least a subset of the data. The method also includes regenerating the data from at least the cache, wherein the regenerated data includes a second portion of the data. The method also includes programming, in a second phase, the regenerated data in a second-level cell mode based on a mapping from the first-level cell mode to the second-level cell mode. The mapping maps each state distribution in the first-level cell mode to at least two non-adjacent state distributions in the second-level cell mode, and a width of each state distribution in the first-level cell mode may be narrowed.

Abstract: Disclosed are systems and methods for providing multi-phased programming with balanced Gray coding. A method includes programming, in a first phase, a first portion of data into memory cells of a flash memory in a first-level cell mode. The method also includes retaining, in a cache, at least a subset of the data. The method also includes regenerating the data from at least the cache, wherein the regenerated data includes a second portion of the data. The method also includes programming, in a second phase, the regenerated data in a second-level cell mode based on a mapping from the first-level cell mode to the second-level cell mode. The mapping maps each state distribution in the first-level cell mode to at least two non-adjacent state distributions in the second-level cell mode, and a width of each state distribution in the first-level cell mode may be narrowed.

Abstract: Disclosed are systems and methods for providing multi-phased programming with balanced Gray coding. A method includes programming, in a first phase, a first portion of data into memory cells of a flash memory in a first-level cell mode. The method also includes retaining, in a cache, at least a subset of the data. The method also includes regenerating the data from at least the cache, wherein the regenerated data includes a second portion of the data. The method also includes programming, in a second phase, the regenerated data in a second-level cell mode based on a mapping from the first-level cell mode to the second-level cell mode. The mapping maps each state distribution in the first-level cell mode to at least two non-adjacent state distributions in the second-level cell mode, and a width of each state distribution in the first-level cell mode may be narrowed.

Abstract: A data storage system stores a set of codewords in memory. The set of codewords are encoded in accordance with a joint nesting matrix specifying multiple layers of integrated interleaved codes, including first, second and third layers of integrated interleaved codes, and the set of codewords stored in the memory include first, second and third layers of parity information corresponding to the first, second and third layers of integrated interleaved codes. When decoding a first codeword and a first subgroup containing the first codeword fail, the system decodes a group of codewords that include two more subgroups of codewords, including the first subgroup of codewords, using the third layer parity information for the group of codewords. The second and third layers of integrated interleaved codes are configured to enable decoding of two codewords, in a subgroup of codewords, having errors beyond the correction capability of the first layer codes.

Abstract: In an illustrative example, a data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an erasure correcting code engine configured to generate first erasure recovery data and temporary erasure recovery data in a volatile memory at least partially based on first data to be written to the non-volatile memory. The first erasure recovery data is configured to enable a first type of data recovery of the first data, and the temporary erasure recovery data is configured to enable a second type of data recovery of the first data. The controller is further configured to store the first erasure recovery data and the temporary erasure recovery data in the volatile memory and, after verifying that the first data is stored in the non-volatile memory, to discard or modify the temporary erasure recovery data.

Abstract: A memory system (e.g., a solid state drive, or SSD) uses application-aware ECC schemes to make use of the specifics of a database schema and analytic queries. Only the fields relevant to the query are decoded, other fields are largely ignored. Integrated interleaved (II) codes and product codes approaches are described. Compared to traditional ECC schemes that decode the entire records before any fields to be used by the analytics are available, the new application-aware ECC schemes may achieve orders of magnitudes throughput improvement and/or substantially lower decoder complexity.

Abstract: A data storage system stores a set of codewords in memory. The set of codewords are encoded in accordance with a joint nesting matrix specifying multiple layers of integrated interleaved codes, including first, second and third layers of integrated interleaved codes, and the set of codewords stored in the memory include first, second and third layers of parity information corresponding to the first, second and third layers of integrated interleaved codes. When decoding a first codeword and a first subgroup containing the first codeword fail, the system decodes a group of codewords that include two more subgroups of codewords, including the first subgroup of codewords, using the third layer parity information for the group of codewords. The second and third layers of integrated interleaved codes are configured to enable decoding of two codewords, in a subgroup of codewords, having errors beyond the correction capability of the first layer codes.

Abstract: In an illustrative example, a method includes receiving data that includes a set of data symbols. The method further includes generating a set of parity symbols based on the set of data symbols using an erasure correcting code. The set of parity symbols includes at least a first parity symbol that is generated based on a first proper subset of the set of data symbols. The first parity symbol enables recovery of a data symbol of the first proper subset independently of a second proper subset of the set of data symbols.

Abstract: In an illustrative example, a decoder includes a variable node unit (VNU) that includes a variable-to-check lookup table circuit configured to output a variable-to-check message corresponding to a check node. The VNU also includes a hard-decision lookup table circuit configured to output a hard decision value corresponding to a variable node. The decoder also includes a check node unit (CNU) responsive to the variable-to-check message and configured to generate an updated check-to-variable message.

Abstract: In an illustrative example, a decoder includes a variable node unit (VNU) that includes a variable-to-check lookup table circuit configured to output a variable-to-check message corresponding to a check node. The VNU also includes a hard-decision lookup table circuit configured to output a hard decision value corresponding to a variable node. The decoder also includes a check node unit (CNU) responsive to the variable-to-check message and configured to generate an updated check-to-variable message.

Abstract: In an illustrative example, a data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an erasure correcting code engine configured to generate first erasure recovery data and temporary erasure recovery data in a volatile memory at least partially based on first data to be written to the non-volatile memory. The first erasure recovery data is configured to enable a first type of data recovery of the first data, and the temporary erasure recovery data is configured to enable a second type of data recovery of the first data. The controller is further configured to store the first erasure recovery data and the temporary erasure recovery data in the volatile memory and, after verifying that the first data is stored in the non-volatile memory, to discard or modify the temporary erasure recovery data.