Abstract: Disclosed are method and an apparatus for analysis of an interface state of a MIS-HEMT device.

Abstract: Disclosed are method and an apparatus for analysis of an interface state of a MIS-HEMT device.

Abstract: A method and apparatus for selecting an integrated circuit device neural network modeling sample; for an input variable having the largest mean impact value, by means of continually and equally dividing an interval of the input variable, until relative errors of all divided intervals are equal to or less than a preset error precision, only at which point the equal division action stops, and the length of the divided interval having the smallest length being taken as a step length of the output variable; the step lengths of other input variables then being respectively calculated, according to the step length of the input variable; and finally, for each input variable, points being extracted according to a change interval and the step length thereof, thereby obtaining a sample point set of each input variable.

Abstract: A method and apparatus for selecting an integrated circuit device neural network modeling sample; for an input variable having the largest mean impact value, by means of continually and equally dividing an interval of the input variable, until relative errors of all divided intervals are equal to or less than a preset error precision, only at which point the equal division action stops, and the length of the divided interval having the smallest length being taken as a step length of the output variable; the step lengths of other input variables then being respectively calculated, according to the step length of the input variable; and finally, for each input variable, points being extracted according to a change interval and the step length thereof, thereby obtaining a sample point set of each input variable.

Abstract: A tunneling field effect transistor, comprising a gate electrode layer, a gate dielectric layer, a source region, a connected region and a drain region, wherein the source region comprises a first source region and a second source region, the second source region comprising an inner layer source region and an outer layer source region. The connected region comprises an expansion region and a high-resistance region. The doping types of materials of the inner layer source and the outer layer source region are opposite, and the forbidden bandwidth of the material of the inner layer source region is less than that of the outer layer source region. The contact surface formed by way of covering the inner layer source region by the outer layer source region is a curved surface.

Abstract: A tunneling field effect transistor, comprising a gate electrode layer, a gate dielectric layer, a source region, a connected region and a drain region, wherein the source region comprises a first source region and a second source region, the second source region comprising an inner layer source region and an outer layer source region. The connected region comprises an expansion region and a high-resistance region. The doping types of materials of the inner layer source and the outer layer source region are opposite, and the forbidden bandwidth of the material of the inner layer source region is less than that of the outer layer source region. The contact surface formed by way of covering the inner layer source region by the outer layer source region is a curved surface.