Patents by Inventor Xinning Liu
Xinning Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11290009Abstract: A high energy efficiency switched-capacitor power converter includes the transmission gates T1-T7, the capacitors C1-C4, the load capacitor CL, and resistors, PMOS tubes and NMOS tubes. The power converter converts a stable input voltage of 3V into an output voltage of 1V by means of charge transfer. In the state of timing sequence 1, the on-chip capacitor C1, the capacitor C2 and the load capacitor CL are charged in series. In the state of timing sequence 2, the capacitor C1 and the capacitor C2 are connected in parallel to the capacitor CL to supplement the charge loss due to load for the capacitor CL. When the establishment is completed, the voltages across the capacitor C1, the capacitor C2, and the capacitor CL are basically the same. At this time, the voltage drop across the switch tube approximates 0 V during the charge transfer process.Type: GrantFiled: April 30, 2020Date of Patent: March 29, 2022Assignee: SOUTHEAST UNIVERSITYInventors: Chao Chen, Jun Yang, Xinning Liu
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Patent number: 11196335Abstract: An ultra-low-power mode control circuit for a power converter includes four modules: a level shift circuit, a start circuit, a static clamp circuit, and a control circuit. When a chip is powered on and a core voltage has not been established, the control circuit firstly starts a power source built-in clock to support operation of the power converter. When the core voltage is established, the control circuit determines whether to switch to an external clock according to a level of a mode selection signal. After the core voltage is powered down, the control circuit automatically wakes up the built-in clock to work.Type: GrantFiled: April 30, 2020Date of Patent: December 7, 2021Assignee: SOUTHEAST UNIVERSITYInventors: Chao Chen, Jun Yang, Xinning Liu
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Patent number: 11190140Abstract: A wide voltage trans-impedance amplifier includes a first P-channel metal oxide semiconductor (PMOS) transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a first bias voltage VB1, a second bias voltage VB2, a third bias voltage VB3, a first N-channel metal oxide semiconductor (NMOS) transistor NM1, and a second NMOS transistor NM2. A common-gate amplifier detects a change of an input voltage, and a negative feedback is constructed by injecting a current into a current mirror to achieve a low input impedance. The trans-impedance amplifier uses a common-gate amplifier to monitor an input voltage and uses a current mirror to perform the transconductance enhancement on an input transistor, while ensuring a relatively high loop gain.Type: GrantFiled: April 30, 2020Date of Patent: November 30, 2021Assignee: SOUTHEAST UNIVERSITYInventors: Chao Chen, Jun Yang, Xinning Liu
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Patent number: 11175686Abstract: A low-temperature drift ultra-low-power linear regulator includes eight PMOS transistors, two resistors, two capacitors and three NMOS transistors. The eight PMOS transistors include PMOS transistor PM1 to PMOS transistor PM8. The two resistors include resistor R1 and resistor R2. The two capacitors include capacitor C1 and capacitor C2. The three NMOS transistors include NMOS transistor NM1, NMOS transistor NM2 and NMOS transistor NM3. From right to left, the linear regulator includes a PTAT voltage core starting circuit, a PTAT voltage core circuit, a negative temperature characteristic generating circuit and a driver stage closed-loop control circuit. PM5-PM8 form a feedback circuit. The feedback circuit clamps the current flowing through PM6 to be proportional to PM2 to obtain a temperature-stable output voltage, and can dynamically adjust the gate voltage of PM5 according to the change of load current to output different currents according to the load demand.Type: GrantFiled: April 30, 2020Date of Patent: November 16, 2021Assignee: SOUTHEAST UNIVERSITYInventors: Chao Chen, Jun Yang, Xinning Liu
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Publication number: 20210351693Abstract: A high energy efficiency switched-capacitor power converter includes the transmission gates T1-T7, the capacitors C1-C4, the load capacitor CL, and resistors, PMOS tubes and NMOS tubes. The power converter converts a stable input voltage of 3V into an output voltage of 1V by means of charge transfer. In the state of timing sequence 1, the on-chip capacitor C1, the capacitor C2 and the load capacitor CL are charged in series. In the state of timing sequence 2, the capacitor C1 and the capacitor C2 are connected in parallel to the capacitor CL to supplement the charge loss due to load for the capacitor CL. When the establishment is completed, the voltages across the capacitor C1, the capacitor C2, and the capacitor CL are basically the same. At this time, the voltage drop across the switch tube approximates 0 V during the charge transfer process.Type: ApplicationFiled: April 30, 2020Publication date: November 11, 2021Applicant: SOUTHEAST UNIVERSITYInventors: Chao CHEN, Jun YANG, Xinning LIU
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Publication number: 20210344266Abstract: An ultra-low-power mode control circuit for a power converter includes four modules: a level shift circuit, a start circuit, a static clamp circuit, and a control circuit. When a chip is powered on and a core voltage has not been established, the control circuit firstly starts a power source built-in clock to support operation of the power converter. When the core voltage is established, the control circuit determines whether to switch to an external clock according to a level of a mode selection signal. After the core voltage is powered down, the control circuit automatically wakes up the built-in clock to work.Type: ApplicationFiled: April 30, 2020Publication date: November 4, 2021Applicant: SOUTHEAST UNIVERSITYInventors: Chao CHEN, Jun YANG, Xinning LIU
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Publication number: 20210320624Abstract: A wide voltage trans-impedance amplifier includes a first P-channel metal oxide semiconductor (PMOS) transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a first bias voltage VB1, a second bias voltage VB2, a third bias voltage VB3, a first N-channel metal oxide semiconductor (NMOS) transistor NM1, and a second NMOS transistor NM2. A common-gate amplifier detects a change of an input voltage, and a negative feedback is constructed by injecting a current into a current mirror to achieve a low input impedance. The trans-impedance amplifier uses a common-gate amplifier to monitor an input voltage and uses a current mirror to perform the transconductance enhancement on an input transistor, while ensuring a relatively high loop gain.Type: ApplicationFiled: April 30, 2020Publication date: October 14, 2021Applicant: SOUTHEAST UNIVERSITYInventors: Chao CHEN, Jun YANG, Xinning LIU
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Publication number: 20210311514Abstract: A low-temperature drift ultra-low-power linear regulator includes eight PMOS transistors, two resistors, two capacitors and three NMOS transistors. The eight PMOS transistors include PMOS transistor PM1 to PMOS transistor PM8. The two resistors include resistor R1 and resistor R2. The two capacitors include capacitor C1 and capacitor C2. The three NMOS transistors include NMOS transistor NM1, NMOS transistor NM2 and NMOS transistor NM3. From right to left, the linear regulator includes a PTAT voltage core starting circuit, a PTAT voltage core circuit, a negative temperature characteristic generating circuit and a driver stage closed-loop control circuit. PM5-PM8 form a feedback circuit. The feedback circuit clamps the current flowing through PM6 to be proportional to PM2 to obtain a temperature-stable output voltage, and can dynamically adjust the gate voltage of PM5 according to the change of load current to output different currents according to the load demand.Type: ApplicationFiled: April 30, 2020Publication date: October 7, 2021Applicant: SOUTHEAST UNIVERSITYInventors: Chao CHEN, Jun YANG, Xinning LIU
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Patent number: 10422883Abstract: A positioning method using height-constraint-based extended Kalman filter, suitable for a GNSS navigation and positioning system, comprises: obtaining an estimated state value of a current epoch by using an extended Kalman filter algorithm and according to an estimated state value of a previous epoch; constraining a positioning height of the current epoch by establishing a height constraint condition, so as to obtain an optimum estimated value of the current epoch and a corresponding mean square error, wherein the optimum estimated value satisfies the height constraint condition; further correcting the estimated state value by using a pseudorange obtained from the mean square error and a measured Doppler shift residual to obtain a final estimated state value of the current epoch, thus more accurately obtaining positioning information of a target to be positioned in the current epoch and enhancing the accuracy of GNSS navigation and positioning.Type: GrantFiled: June 27, 2016Date of Patent: September 24, 2019Assignee: SOUTHEAST UNIVERSITYInventors: Yuan Zhuang, Jinfeng Ma, Longning Qi, Xinning Liu, Jun Yang
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Publication number: 20190146095Abstract: A positioning method using height-constraint-based extended Kalman filter, suitable for a GNSS navigation and positioning system, comprises: obtaining an estimated state value of a current epoch by using an extended Kalman filter algorithm and according to an estimated state value of a previous epoch; constraining a positioning height of the current epoch by establishing a height constraint condition, so as to obtain an optimum estimated value of the current epoch and a corresponding mean square error, wherein the optimum estimated value satisfies the height constraint condition; further correcting the estimated state value by using a pseudorange obtained from the mean square error and a measured. Doppler shift residual to obtain a final estimated state value of the current epoch, thus more accurately obtaining positioning information of a target to be positioned in the current epoch and enhancing the accuracy of GNSS navigation and positioning.Type: ApplicationFiled: June 27, 2016Publication date: May 16, 2019Applicant: Southeast UniversityInventors: YUAN ZHUANG, JINFENG MA, LONGNING QI, XINNING LIU, JUN YANG
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Patent number: 9236115Abstract: A circuit for improving process robustness of sub-threshold SRAM memory cells serves as an auxiliary circuit for a sub-threshold SRAM memory cell. The output of the circuit is connected to PMOS transistors of the sub-threshold SRAM memory cell and substrate of PMOS transistors in the circuit. The circuit includes a detection circuit for threshold voltages of the PMOS transistors and a differential input and single-ended output amplifier. The circuit changes the substrate voltage of the PMOS transistors in the sub-threshold SRAM memory cell and the PMOS transistors in the circuit in a self-adapting manner by detecting threshold voltage fluctuations of PMOS and NMOS transistor resulted from process fluctuations and thereby regulates the threshold voltages of the PMOS transistors, so that the threshold voltages of the PMOS and NMOS transistors match. The circuit improves the noise margin of sub-threshold SRAM memory cells and the process robustness of sub-threshold SRAM memory cells.Type: GrantFiled: December 27, 2012Date of Patent: January 12, 2016Assignee: Southeast UniversityInventors: Na Bai, Longxing Shi, Jun Yang, Xinning Liu, Jiafeng Zhu, Yue Feng, Cai Gong, Fei Pan, Hong Chang, Yifeng Deng, Yuan Chen, Yingcheng Xia
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Publication number: 20150008971Abstract: Disclosed is a noise current compensation circuit. The circuit is provided with two input and output terminals A and B, and two control terminals CON and CONF. The control terminals control a work mode (work state and pre-charge state) of the compensation circuit. The compensation circuit consists of 7 PMOS transistors and 8 NMOS transistors. In the normal work state, by detecting changes of potential change rate of two signal lines in an original circuit, the noise current compensation circuit automatically enables one end of the original circuit that discharges slowly to discharge a signal more slowly, and enables one end of the original circuit that discharges rapidly to discharge a signal more rapidly, thus eliminating the influence of the noise current on the circuit and providing assistance for correct identification of subsequent circuit signals.Type: ApplicationFiled: December 27, 2012Publication date: January 8, 2015Inventors: Na Bai, Longxing Shi, Jun Yang, Xinning Liu, Jiafeng Zhu, Yue Feng, Cai Gong, Fei Pan, Hong Chang, Yifeng Deng, Yuan Chen, Yingcheng Xia
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Patent number: 8922265Abstract: Disclosed is a noise current compensation circuit. The circuit is provided with two input and output terminals A and B, and two control terminals CON and CONF. The control terminals control a work mode (work state and pre-charge state) of the compensation circuit. The compensation circuit consists of 7 PMOS transistors and 8 NMOS transistors. In the normal work state, by detecting changes of potential change rate of two signal lines in an original circuit, the noise current compensation circuit automatically enables one end of the original circuit that discharges slowly to discharge a signal more slowly, and enables one end of the original circuit that discharges rapidly to discharge a signal more rapidly, thus eliminating the influence of the noise current on the circuit and providing assistance for correct identification of subsequent circuit signals.Type: GrantFiled: December 27, 2012Date of Patent: December 30, 2014Assignee: Southeast UniversityInventors: Na Bai, Longxing Shi, Jun Yang, Xinning Liu, Jiafeng Zhu, Yue Feng, Cai Gong, Fei Pan, Hong Chang, Yifeng Deng, Yuan Chen, Yingcheng Xia
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Publication number: 20140376305Abstract: The present invention discloses a circuit for improving process robustness of sub-threshold SRAM memory cells, which serves as an auxiliary circuit for a sub-threshold SRAM memory cell. The output of the circuit is connected to the PMOS tube of the sub-threshold SRAM memory cell and the substrate of a PMOS tube in the circuit. The circuit comprises a detection circuit for threshold voltage of PMOS tube and a differential input and single-ended output amplifier. The circuit changes the substrate voltage of the PMOS tubes in the sub-threshold SRAM memory cell and the substrate voltage of the PMOS tube in the circuit in a self-adapting manner by detecting threshold voltage fluctuations of PMOS tubes and NMOS tubes resulted from process fluctuations and thereby regulate the threshold voltages of the PMOS tubes, so that the threshold voltage of PMOS tubes matches the threshold voltage of NMOS tubes.Type: ApplicationFiled: December 27, 2012Publication date: December 25, 2014Inventors: Na Bai, Longxing Shi, Jun Yang, Xinning Liu, Jiafeng Zhu, Yue Feng, Cai Gong, Fei Pan, Hong Chang, Yifeng Deng, Yuan Chen, Yingcheng Xia
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Patent number: 8909999Abstract: A dynamic voltage scaling system based on on-chip monitoring and voltage prediction is disclosed, comprising a main circuit that has integrated on-chip monitoring circuits, a supply voltage scaling module, and voltage converters, wherein, the supply voltage scaling module comprises a sampling and statistics module designed to calculate the error rate of the main circuit in the current time slice, a state recording module designed to record the error rate and the corresponding supply voltage, an error prediction module, and a state transition probability generation module; the error prediction module predicts the error trend of the main circuit in a future time slice according to the state recording module and the state transition probability generation module, and generates regulation signals and sends to the corresponding voltage converters, so as to generate the voltage required for operation of the entire main circuit.Type: GrantFiled: October 17, 2011Date of Patent: December 9, 2014Assignee: Southeast UniversityInventors: Longxing Shi, Weiwei Shan, Jun Yang, Haolin Gu, Xinning Liu, Yang Zhang
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Patent number: 8703975Abstract: The present invention designs and synthesizes the ascorbyl ester derivatives of the aryl (ethanoic) propanoic acid non-steroidal anti-inflammatory medicaments, such as ibuprofen, ketoprofen and naproxen, and addition salt of the derivatives with pharmaceutical acid or pharmaceutical alkaline. The non-steroidal anti-inflammatory medicament which takes the ibuprofen as the representative is a common antipyretic analgesic medicament. The invention has remarkable antipyretic and analgesic effects and good safety except for anti-inflammatory effect, thus being not only suitable for adults, but also suitable for the elderly people, infants and children.Type: GrantFiled: December 24, 2009Date of Patent: April 22, 2014Assignees: Wuxi Hongrui Bio-Pharma-Tech Co., Ltd.Inventors: Luhong Tang, Ajuan Dai, Ze Wang, Yang Sun, Xinning Liu, Lingyan Xu, Xin Fang, Shuang Qiu, Yaqing Cao, Xiaomin Xu, Ruixia Jiang, Chao Wu
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Publication number: 20130154583Abstract: The present invention discloses a dynamic voltage scaling system based on on-chip monitoring and voltage prediction, comprising a main circuit that has integrated on-chip monitoring circuits, a supply voltage scaling module, and voltage converters, wherein, the supply voltage scaling module comprises a sampling and statistics module designed to calculate the error rate of the main circuit in the current time slice, a state recording module designed to record the error rate and the corresponding supply voltage, an error prediction module, and a state transition probability generation module; the error prediction module predicts the error trend of the main circuit in a future time slice according to the state recording module and the state transition probability generation module, and generates regulation signals and sends to the corresponding voltage converters, so as to generate the voltage required for operation of the entire main circuit.Type: ApplicationFiled: October 17, 2011Publication date: June 20, 2013Applicant: SOUTHEAST UNIVERSITYInventors: Longxing Shi, Weiwei Shan, Jun Yang, Haolin Gu, Xinning Liu, Yang Zhang
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Publication number: 20120115897Abstract: The present invention designs and synthesizes the ascorbyl ester derivatives of the aryl (ethanoic) propanoic acid non-steroidal anti-inflammatory medicaments, such as ibuprofen, ketoprofen and naproxen, and addition salt of the derivatives with pharmaceutical acid or pharmaceutical alkaline. The non-steroidal anti-inflammatory medicament which takes the ibuprofen as the representative is a common antipyretic analgesic medicament. The invention has remarkable antipyretic and analgesic effects and good safety except for anti-inflammatory effect, thus being not only suitable for adults, but also suitable for the elderly people, infants and children.Type: ApplicationFiled: December 24, 2009Publication date: May 10, 2012Applicants: WUXI HONGRUI BIO-PHARMA-TECH CO., LTD .Inventors: Luhong Tang, Ajuan Dai, Ze Wang, Yang Sun, Xinning Liu, Lingyan Xu, Xin Fang, Shuang Qiu, Yaqing Cao, Xiaomin Xu, Ruixia Jiang, Chao Wu