Abstract: Integrated circuit structures having front side signal lines and backside power delivery are described. In an example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack or fin channel structures within a cell boundary. A plurality of trench contacts is extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A first signal line, a second signal line, a third signal line, and a fourth signal line are over the plurality of gate lines and the plurality of trench contacts within the cell boundary. A backside power delivery line is coupled to one of the plurality of trench contacts within the cell boundary.

Abstract: An integrated circuit includes a first device having a first source or drain region, and a second device having a second source or drain region that is laterally adjacent to the first source or drain region. A conductive source or drain contact includes (i) a lower portion in contact with the first source or drain region, and extending above the first source or drain region, and (ii) an upper portion extending laterally from above the lower portion to above the second source or drain region. A dielectric material is between at least a section of the upper portion of the conductive source or drain contact and the second source or drain region. In an example, each of the first and second devices is a gate-all-around (GAA) device having one or more nanoribbons, nanowires, or nanosheets as channel regions, or is a finFet structure having a fin-based channel region.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques for providing a metal routing layer zero (M0) track within a circuit structure that had a width that overlaps both PMOS and NMOS within the circuit structure. There may be three M0 routing tracks, with a first of the M0 routing tracks directly over PMOS, a second of the M0 routing tracks directly over NMOS, and a third of the M0 routing tracks over a portion separating PMOS and NMOS and overlapping both PMOS and NMOS. The wide second routing track will allow efficient electrical coupling between a device on the PMOS and a device on the NMOS. Other embodiments may be described and/or claimed.

Abstract: Integrated circuit structures having gate cut offset, and methods of fabricating integrated circuit structures having gate cut offset, are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowires. A second vertical stack of horizontal nanowires is spaced apart from and parallel with the first vertical stack of horizontal nanowires. A gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, a second gate structure over the second vertical stack of horizontal nanowires, and a gate cut between the first gate structure portion and the second gate structure portion, the gate cut laterally closer to the second vertical stack of horizontal nanowires than to the first vertical stack of horizontal nanowires.

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to standard cell architectures without power delivery space allocation. Other embodiments may be described or claimed.

Abstract: Integrated circuit structures having gate cut offset, and methods of fabricating integrated circuit structures having gate cut offset, are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowires. A second vertical stack of horizontal nanowires is spaced apart from and parallel with the first vertical stack of horizontal nanowires. A gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, a second gate structure over the second vertical stack of horizontal nanowires, and a gate cut between the first gate structure portion and the second gate structure portion, the gate cut laterally closer to the second vertical stack of horizontal nanowires than to the first vertical stack of horizontal nanowires.

Abstract: Techniques are provided herein to form an integrated circuit with a double-height standard cell layout that can utilize both frontside and backside connections. The layout involves merging two of the transistors into a single wider transistor that extends along the midline of the double-height standard cell layout. Accordingly, the double-height standard cell layout may include three total transistors with one transistor being wider than the other two. The transistors may be configured as an inverter with enhanced driving capability in the double height standard cell layout. The wider transistor at the center of the double-height standard cell layout includes a source or drain region with both a topside contact and a backside contact to provide additional interconnect routing flexibility. The double-height standard cell may include an n-channel device having a first width aligned along a centerline of the double-height standard cell and two p-channel devices or vice versa.

Abstract: Multifunctional PSMA targeted conjugate compounds, pharmaceutical compositions comprising these compounds, use of the compounds for treating and detecting cancers in a subject are described herein.

Abstract: PSMA targeted conjugate compounds, pharmaceutical compositions comprising these compounds, methods for treating and detecting cancers in a subject, methods for identifying cancer cells in a sample are described herein.

Abstract: PSMA targeted conjugate compounds, pharmaceutical compositions comprising these compounds, methods for treating and detecting cancers in a subject, methods for identifying cancer cells in a sample are described herein.

Abstract: Prostate-specific membrane antigen (PSMA) targeted compounds having formula (I), nanoclusters formed thereof, pharmaceutical compositions comprising a plurality of these compounds, and methods for treating and detecting cancers in a subject are described herein.

Abstract: PSMA targeted compounds, pharmaceutical compositions comprising these compounds, and methods for treating and detecting cancers in a subject are described herein.

Abstract: Techniques are described for designing and forming cells comprising transistor devices for an integrated circuit. In an example, an integrated circuit structure includes a plurality of cells arranged in rows where some rows have different cell heights compared to other rows. Additionally, the various rows of cells may contain semiconductor nanoribbons having different widths between different rows. For example, any number of first rows of cells can each have a first height and any number of second rows can each have a second height that is smaller than the first height. The first rows of cells may include transistors with semiconductor nanoribbons having a first width and the second rows of cells may include transistors with semiconductor nanoribbons having a second width smaller than the first width. In some cases, any of the first rows of cells may also include transistors with semiconductor nanoribbons having the second width.

Abstract: Techniques are described for designing and forming cells having transistor devices. In an example, an integrated circuit structure includes a plurality of cells where adjacent cells have a decreased distance between them along their height and a staggered via arrangement. Accordingly, a first cell may be adjacent to a second cell along a shared cell boundary. A first via is provided between a first gate structure of the first cell adjacent to the cell boundary and a first metal layer above the first gate structure, and a second via is provided between a second gate structure of the second cell adjacent to the cell boundary and a second metal layer above the second gate structure. No part of the first via is aligned with any part of the second via along the first direction.

Abstract: PSMA targeted anticancer agent-phthalocyanine conjugate compounds, pharmaceutical compositions comprising these compounds, methods for treating and detecting cancers in a subject.

Abstract: PSMA targeted conjugate compounds, pharmaceutical compositions comprising these compounds, methods for treating and detecting cancers in a subject, methods for identifying cancer cells in a sample are described herein.

Abstract: Prostate-specific membrane antigen (PSMA) targeted compounds having formula (I), nanoclusters formed thereof, pharmaceutical compositions comprising a plurality of these compounds, and methods for treating and detecting cancers in a subject are described herein.

Abstract: Integrated circuit structures having front side signal lines and backside power delivery are described. In an example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack or fin channel structures within a cell boundary. A plurality of trench contacts is extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A first signal line, a second signal line, a third signal line, and a fourth signal line are over the plurality of gate lines and the plurality of trench contacts within the cell boundary. A backside power delivery line is coupled to one of the plurality of trench contacts within the cell boundary.

Abstract: Integrated circuit structures having front side signal lines and backside power delivery are described. In an example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack or fin channel structures within a cell boundary. A plurality of trench contacts is extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A first signal line, a second signal line, a third signal line, and a fourth signal line are over the plurality of gate lines and the plurality of trench contacts within the cell boundary. A backside power delivery line is coupled to one of the plurality of trench contacts within the cell boundary.

Abstract: Transistor cell architectures have three MO routing tracks within a single cell height. The cell architectures include at least one p-type transistor formed over a p-type diffusion region and at least one n-type transistor formed over an n-type diffusion region. Each diffusion region extends primarily in a particular direction, and the MO routing tracks extending in the same direction as the diffusion regions. One MO routing track may be formed over each of the diffusion regions, and a third MO routing track formed between the diffusion regions.