Abstract: A charging system may include a plurality of power modules, a distributing switch module, and a plurality of charging ports. The distributing switch module includes a first distributing unit and a second distributing unit. The first distributing unit may connect a first part of power modules in the plurality of power modules to a first charging port, to distribute powers of the first part of power modules to the first charging port. The second distributing unit may connect a second part of power modules in the plurality of power modules to a second charging port, to distribute powers of the second part of power modules to the second charging port. Therefore, the first charging port may charge a first terminal, and the second charging port may charge a second terminal.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a substrate, and forming a sacrificial dielectric layer on the substrate; patterning a part of the sacrificial dielectric layer along a first direction, and forming a plurality of first trenches arranged at intervals along a second direction in the sacrificial dielectric layer; patterning a part of the sacrificial dielectric layer at bottoms of the first trenches and a part of the substrate below the part of the sacrificial dielectric layer, and forming a plurality of second trenches arranged at intervals below the first trenches, wherein the second trench has a preset depth in the substrate; forming a protective layer on sidewalls of the first trenches and sidewalls of the second trenches; and forming bit line structures in the first trenches and the second trenches.

Abstract: A charging pile, system and method, the charging pile including N charging branches, wherein each charging branch includes a charging gun, a power module configured to supply power for the charging gun, and an intra-branch switch connected between the charging gun and power module, K charging controllers, wherein each charging controller is connected to at least one intra-branch switch, and is configured to control turn-on and turn-off of the connected intra-branch switch, where N?K?1, M interfaces, configured to connect to one or more charging piles other than the charging pile, where N?M?1, and an interface switch, configured to connect to every two of the M interfaces, where each charging branch is connected to one interface of the M interfaces using an external switch.

Abstract: A method of manufacturing a semiconductor structure and a semiconductor structure are disclosed. The method of manufacturing a semiconductor structure includes: providing a substrate; forming multiple support structures on the substrate, where the multiple support structures are arranged at intervals along a first direction, and a gate trench is formed between every two adjacent support structures; forming a gate structure in the gate trench; and removing a part of each of the support structures, such that each of retained support structures forms two isolation sidewalls spaced apart, the two isolation sidewalls are arranged on opposite sidewalls of the adjacent gate structures respectively, and a filling region is formed by the two isolation sidewalls.

Abstract: Disclosed is a method for manufacturing a contact hole, a semiconductor structure and electronic equipment. The method includes: forming a mask layer on an upper end face of a first oxide layer of the semiconductor structure, and exposing a pattern of a target contact hole on the mask layer; exposing a portion, corresponding to a target contact hole, of an upper end face of a contact layer and a portion, corresponding to the target contact hole, of an upper end face of an upper layer structure; depositing a second insulation layer on an etched surface, and depositing a second oxide layer on the second insulation layer; and removing portions, above the upper end face of the first oxide layer, of the second insulation layer and the second oxide layer, and removing a part of the contact layer, and exposing an upper end face of a zeroth layer contact.

Abstract: The present disclosure relates to the field of semiconductor technologies, and provides a semiconductor structure and a semiconductor structure manufacturing method. The semiconductor structure includes a substrate, a bitline, a bitline isolator, a peripheral gate and a gate isolator. A plurality of active regions are formed in the substrate. The bitline is located on the substrate and connected to the active region. The bitline isolator is located on the substrate and covers a sidewall of the bitline. The bitline isolator includes a first air gap. The peripheral gate is located on the substrate. The gate isolator is located on the substrate and covers a sidewall of the peripheral gate. The gate isolator includes a second air gap.