Abstract: Embodiments of the present disclosure are directed to a gate drive circuit and a display panel. The gate drive circuit includes a plurality of cascaded gate drive units. The N-level gate drive unit includes a pull-up transistor, a touch transistor, and a voltage holding circuit. An input end of the voltage holding circuit is connected with a high potential line, a first control end of the voltage holding circuit is connected with a touch line, a second control end of the voltage holding circuit is connected with a pull-up node, and an output end of the voltage holding circuit is connected with the pull-up node. The display panel includes a common voltage line and the gate drive circuit mentioned above, thereby alleviating the technical problem of unstable potential of pull-up nodes during a touch stage.

Abstract: A gate driver on array (GOA) circuit includes a plurality of GOA units in cascade. Each of the GOA units includes a pull-up control module, a pull-up module, a capacitor module, pull-down maintenance module, a pull-down module, and a GOA drive shutdown module. The pull-up control module is connected to a signal output terminal G(N?3) of a (N?3) stage GOA unit, a constant-voltage high-potential signal terminal, and a first node, wherein N is a natural number. The gate shutdown signal terminal is configured to provide a low potential signal during a display period and is configured to provide a high potential signal during a touch period, when the gate shutdown signal terminal provides the low potential signal, the pull-down maintenance module maintains a pull-down maintenance function, and when the gate shutdown signal terminal provides the high potential signal, the pull-down maintenance module becomes is disabled.

Abstract: A gate driver on array (GOA) circuit includes a plurality of GOA units in cascade. Each of the GOA units includes a pull-up control module, a pull-up module, a capacitor module, pull-down maintenance module, a pull-down module, and a GOA drive shutdown module. The pull-up control module is connected to a signal output terminal G(N?3) of a (N?3) stage GOA unit, a constant-voltage high-potential signal terminal, and a first node, wherein N is a natural number. The gate shutdown signal terminal is configured to provide a low potential signal during a display period and is configured to provide a high potential signal during a touch period, when the gate shutdown signal terminal provides the low potential signal, the pull-down maintenance module maintains a pull-down maintenance function, and when the gate shutdown signal terminal provides the high potential signal, the pull-down maintenance module becomes is disabled.

Abstract: Embodiments of the present disclosure are directed to a gate drive circuit and a display panel. The gate drive circuit includes a plurality of cascaded gate drive units. The N-level gate drive unit includes a pull-up transistor, a touch transistor, and a voltage holding circuit. An input end of the voltage holding circuit is connected with a high potential line, a first control end of the voltage holding circuit is connected with a touch line, a second control end of the voltage holding circuit is connected with a pull-up node, and an output end of the voltage holding circuit is connected with the pull-up node. The display panel includes a common voltage line and the gate drive circuit mentioned above, thereby alleviating the technical problem of unstable potential of pull-up nodes during a touch stage.

Abstract: An array substrate includes a first electrode, scanning lines extending along a first direction, data lines, and common signal lines. The data lines and the common signal lines extend along a second direction. The first electrode includes a first and a second sub-electrode. Each data line is disposed between two common signal lines. Two scanning lines, two common signal lines, and a data line define a first and a second sub-pixel area. The first and the second sub-electrode are disposed within the first and the second sub-pixel area respectively. The first sub-electrode includes a first main portion disposed close to a common signal line and first branch portions spaced along the second direction. A first space is defined between two adjacent first branch portions. Ends of the first branch portions are connected to the first main portion. Another ends of the first branch portions are spaced with a first space.

Abstract: An array substrate includes a first electrode, scanning lines extending along a first direction, data lines, and common signal lines. The data lines and the common signal lines extend along a second direction. The first electrode includes a first and a second sub-electrode. Each data line is disposed between two common signal lines. Two scanning lines, two common signal lines, and a data line define a first and a second sub-pixel area. The first and the second sub-electrode are disposed within the first and the second sub-pixel area respectively. The first sub-electrode includes a first main portion disposed close to a common signal line and first branch portions spaced along the second direction. A first space is defined between two adjacent first branch portions. Ends of the first branch portions are connected to the first main portion. Another ends of the first branch portions are spaced with a first space.