Abstract: Two pairs of alignment targets (one aligned, one misaligned by a bias distance) are formed on different masks to produce a first pair of conjugated interference patterns. Other pairs of alignment targets are also formed on the masks to produce a second pair of conjugated interference patterns that are inverted the first. Misalignment of the dark and light regions of first interference patterns and the second interference patterns in both pairs of conjugated interference patterns is determined when patterns formed using the masks are overlaid. A magnification factor (of the interference pattern misalignment to the target misalignment) is calculated as a ratio of the difference of misalignment of the relatively dark and relatively light regions in the pairs of interference patterns, over twice the bias distance. The interference pattern misalignment is divided by the magnification factor to produce a self-referenced and self-calibrated target misalignment amount, which is then output.

Abstract: A method of fabricating fully self-aligned vias includes performing a first deposition process, forming a second dielectric layer, performing a first chemical mechanical polishing (CMP) process, performing a selective removal plasma process to form second vias, performing a second deposition process to deposit an etch stop layer in the second vias, performing a third deposition process, forming a third dielectric layer, performing a second CMP process, performing a first lithography-and-etch process to form third vias in the third dielectric layer, performing a fourth deposition process to form a second metal layer in the third vias, performing a fourth CMP process, performing a fifth deposition process to form a third metal layer of third metal, performing a sixth deposition process to form a second hardmask, performing a second lithography-and-etch process, performing an over etch, performing a seventh deposition process, forming a fourth dielectric layer, performing a fifth CMP process.

Abstract: Two pairs of alignment targets (one aligned, one misaligned by a bias distance) are formed on different masks to produce a first pair of conjugated interference patterns. Other pairs of alignment targets are also formed on the masks to produce a second pair of conjugated interference patterns that are inverted the first. Misalignment of the dark and light regions of first interference patterns and the second interference patterns in both pairs of conjugated interference patterns is determined when patterns formed using the masks are overlaid. A magnification factor (of the interference pattern misalignment to the target misalignment) is calculated as a ratio of the difference of misalignment of the relatively dark and relatively light regions in the pairs of interference patterns, over twice the bias distance. The interference pattern misalignment is divided by the magnification factor to produce a self-referenced and self-calibrated target misalignment amount, which is then output.

Abstract: Two pairs of alignment targets (one aligned, one misaligned by a bias distance) are formed on different masks to produce a first pair of conjugated interference patterns. Other pairs of alignment targets are also formed on the masks to produce a second pair of conjugated interference patterns that are inverted the first. Misalignment of the dark and light regions of the first interference patterns and the second interference patterns in both pairs of conjugated interference patterns is determined when patterns formed using the masks are overlaid. A magnification factor (of the interference pattern misalignment to the target misalignment) is calculated as a ratio of the difference of misalignment of the relatively dark and relatively light regions in the pairs of interference patterns, over twice the bias distance. The interference pattern misalignment is divided by the magnification factor to produce a self-referenced and self-calibrated target misalignment amount, which is then output.

Abstract: In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.

Abstract: Structures for detecting and correcting an overlay inaccuracy and methods of detecting and correcting an overlay inaccuracy. An overlay target includes a first plurality of features arranged along a first longitudinal axis in a first line-space pattern having a first line width, and a second plurality of features arranged along a second longitudinal axis in a second line-space pattern having a second line width that is less than the first line width. The second longitudinal axis is aligned substantially parallel to the first longitudinal axis.

Abstract: Two pairs of alignment targets (one aligned, one misaligned by a bias distance) are formed on different masks to produce a first pair of conjugated interference patterns. Other pairs of alignment targets are also formed on the masks to produce a second pair of conjugated interference patterns that are inverted the first. Misalignment of the dark and light regions of the first interference patterns and the second interference patterns in both pairs of conjugated interference patterns is determined when patterns formed using the masks are overlaid. A magnification factor (of the interference pattern misalignment to the target misalignment) is calculated as a ratio of the difference of misalignment of the relatively dark and relatively light regions in the pairs of interference patterns, over twice the bias distance. The interference pattern misalignment is divided by the magnification factor to produce a self-referenced and self-calibrated target misalignment amount, which is then output.

Abstract: Two pairs of alignment targets (one aligned, one misaligned by a bias distance) are formed on different masks to produce a first pair of conjugated interference patterns. Other pairs of alignment targets are also formed on the masks to produce a second pair of conjugated interference patterns that are inverted the first. Misalignment of the dark and light regions of the first interference patterns and the second interference patterns in both pairs of conjugated interference patterns is determined when patterns formed using the masks are overlaid. A magnification factor (of the interference pattern misalignment to the target misalignment) is calculated as a ratio of the difference of misalignment of the relatively dark and relatively light regions in the pairs of interference patterns, over twice the bias distance. The interference pattern misalignment is divided by the magnification factor to produce a self-referenced and self-calibrated target misalignment amount, which is then output.

Abstract: Embodiments of the disclosure provides an apparatus for aligning layers of an integrated circuit (IC), the apparatus including: an insulator layer positioned above a semiconductor substrate; a first diffraction grating within a first region of the insulator layer, the first diffraction grating including a first grating material within the first region of the insulator layer; and a second diffraction grating within a second region of the insulator layer, the second grating including a second grating material within the second region of the insulator layer, wherein the second grating material is different from the first grating material, and wherein an optical contrast between the first and second grating materials is greater than an optical contrast between the second grating material and the insulator layer.

Abstract: Embodiments of the disclosure provides an apparatus for aligning layers of an integrated circuit (IC), the apparatus including: an insulator layer positioned above a semiconductor substrate; a first diffraction grating within a first region of the insulator layer, the first diffraction grating including a first grating material within the first region of the insulator layer; and a second diffraction grating within a second region of the insulator layer, the second grating including a second grating material within the second region of the insulator layer, wherein the second grating material is different from the first grating material, and wherein an optical contrast between the first and second grating materials is greater than an optical contrast between the second grating material and the insulator layer.

Abstract: In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.

Abstract: In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to overlay structures and methods of manufacture. The method includes locating a first plurality of offset dummy features in a first layer; locating a second plurality of offset dummy features in a second layer; measuring a distance between the first plurality of offset dummy features and the second plurality of offset dummy features; and determining that the first layer or the second layer is shifted with respect to one another based on the measurement.

Abstract: In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.

Abstract: Two pairs of alignment targets (one aligned, one misaligned by a bias distance) are formed on different masks to produce a first pair of conjugated interference patterns. Other pairs of alignment targets are also formed on the masks to produce a second pair of conjugated interference patterns that are inverted the first. Misalignment of the dark and light regions of the first interference patterns and the second interference patterns in both pairs of conjugated interference patterns is determined when patterns formed using the masks are overlaid. A magnification factor (of the interference pattern misalignment to the target misalignment) is calculated as a ratio of the difference of misalignment of the relatively dark and relatively light regions in the pairs of interference patterns, over twice the bias distance. The interference pattern misalignment is divided by the magnification factor to produce a self-referenced and self-calibrated target misalignment amount, which is then output.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to overlay structures and methods of manufacture. The method includes locating a first plurality of offset dummy features in a first layer; locating a second plurality of offset dummy features in a second layer; measuring a distance between the first plurality of offset dummy features and the second plurality of offset dummy features; and determining that the first layer or the second layer is shifted with respect to one another based on the measurement.

Abstract: A method includes forming at least one fin above a semiconductor substrate. An isolation structure is formed adjacent the fin. A liner layer is formed above the isolation structure adjacent an interface between the fin and the isolation structure. The liner layer includes a material different than the isolation structure. A sacrificial gate structure is formed above a portion of the fin and includes a sacrificial gate insulation layer and a sacrificial gate structure. The sacrificial gate structure is removed. The sacrificial gate insulation layer is removed selectively to the liner layer. A replacement gate structure is formed above a portion of the fin in a cavity defined by removing the sacrificial gate structure.

Abstract: Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.

Abstract: A method includes forming a placeholder gate structure embedded in a dielectric layer. The placeholder gate structure includes a sacrificial material. A first hard mask layer is formed above the dielectric layer. The first hard mask layer and the sacrificial material are the same material. A second hard mask layer is formed above the first hard mask layer. The second hard mask layer is patterned to define an opening therein exposing a portion of the first hard mask layer and being disposed above a portion of the placeholder gate structure. The exposed portion of the first hard mask layer and the portion of the sacrificial material of the placeholder gate structure disposed below the opening are removed to define a gate cut cavity and divide the placeholder gate structure into first and second segments. A dielectric material is formed in the gate cut cavity.

Abstract: Methods for forming a gate structure of a circuit structure are provide. The methods for forming the gate structure may include: forming a first gate pattern in a gate mask layer, the forming including a first etching of rounded corner portions of the first gate pattern; forming a second gate pattern in the gate mask layer, the second gate pattern at least partially overlapping the first gate pattern, the forming including a second etching of rounded corner portions of the second gate pattern; and, etching the gate mask layer using the first gate pattern and second gate pattern to form the gate structure.