Abstract: Embodiments of the present invention disclose a data processing apparatus. Output ends of an input switching module in the apparatus are respectively connected to input ends of buffer units included in a buffer module; a control end of a write arbiter is connected to a control end of the input switching module. Input ends of an output switching module are respectively connected to output ends of the buffer units; Output ends of the output switching module are respectively connected to input ends of a rearranger; a control end of a read arbiter is connected to a control end of the output switching module; and output ends of the rearranger are respectively connected to output ends of the data processing apparatus.

Abstract: Embodiments of the present invention disclose a data processing apparatus. Output ends of an input switching module in the apparatus are respectively connected to input ends of cache units included in a cache module; a control end of a write arbiter is connected to a control end of the input switching module; Input ends of an output switching module are respectively connected to output ends of the cache units; Output ends of the output switching module are respectively connected to input ends of a rearranger; a control end of a read arbiter is connected to a control end of the output switching module; and output ends of the rearranger are respectively connected to output ends of the data processing apparatus.

Abstract: The present invention discloses a method for buffering a cell by a crossbar switching matrix, which includes: sending a jitter timestamp to a switching port connected to the crossbar switching matrix through a link, and receiving a cell that is sent by the switching port and carries the jitter timestamp, in which the jitter timestamp indicates a jitter of the link itself; and using a sum of the jitter timestamp carried in the cell and a relative delay timestamp of the corresponding link as a total timestamp, and storing the cell in a buffering unit corresponding to the total timestamp in a cell buffer of the link, in which the relative delay timestamp indicates a difference of a delay of the link relative to a delay of a lowest link.

Abstract: A method and apparatus for allocating storage addresses are disclosed. The method includes: receiving a storage address allocation request; searching a level-2 bitmap in a hierarchical bitmap in bidirectional mode; outputting an idle bit according to the result of searching in the level-2 bitmap; obtaining a storage address according to the output idle bit, and allocating the storage address. The apparatus includes: a first receiving module, configured to receive a storage address allocation request; a first searching module, configured to search a level-2 bitmap in a hierarchical bitmap in bidirectional mode for an idle bit, wherein the hierarchical bitmap includes N level-1 bitmaps and the level-2 bitmap; and an allocating module, configured to: obtain a storage address according to the output idle bit in the level-2 bitmap, and allocate the obtained storage address.

Abstract: The present invention discloses a method for buffering a cell by a crossbar switching matrix, which includes: sending a jitter timestamp to a switching port connected to the crossbar switching matrix through a link, and receiving a cell that is sent by the switching port and carries the jitter timestamp, in which the jitter timestamp indicates a jitter of the link itself; and using a sum of the jitter timestamp carried in the cell and a relative delay timestamp of the corresponding link as a total timestamp, and storing the cell in a buffering unit corresponding to the total timestamp in a cell buffer of the link, in which the relative delay timestamp indicates a difference of a delay of the link relative to a delay of a lowest link.

Abstract: A method and apparatus for allocating storage addresses are disclosed. The method includes: receiving a storage address allocation request; searching a level-2 bitmap in a hierarchical bitmap in bidirectional mode; outputting an idle bit according to the result of searching in the level-2 bitmap; obtaining a storage address according to the output idle bit, and allocating the storage address. The apparatus includes: a first receiving module, configured to receive a storage address allocation request; a first searching module, configured to search a level-2 bitmap in a hierarchical bitmap in bidirectional mode for an idle bit, wherein the hierarchical bitmap includes N level-1 bitmaps and the level-2 bitmap; and an allocating module, configured to: obtain a storage address according to the output idle bit in the level-2 bitmap, and allocate the obtained storage address.