Abstract: Colour component prediction method is provided, which includes that: first reference sample set corresponding to colour component to be predicted of coding block in video image is acquired; when available sample number in first reference sample set is less than preset number, preset component value is taken as predicted value corresponding to the colour component to be predicted; when available sample number in first reference sample set is not less than preset number, first reference sample set is screened to obtain second reference sample set; when available sample number in second reference sample set is equal to preset number, model parameter is determined through second reference sample set, and prediction model corresponding to colour component to be predicted is obtained based on model parameter, prediction model is used for prediction processing of colour component to be predicted to obtain predicted value corresponding to colour component to be predicted.

Abstract: A method for intra prediction includes: obtaining multiple previously reconstructed neighbouring blocks corresponding to a current processing block; determining prediction modes, that are signalled in a bitstream, corresponding to neighbouring blocks of the multiple previously reconstructed neighbouring blocks, to obtain multiple first prediction modes; if the multiple first prediction modes comprise at least two directional modes, taking directional modes comprised in the multiple first prediction modes as first prediction directions; performing, according to a preset operation rule, operation on multiple first prediction directions of the first prediction directions to obtain second prediction directions; obtaining a prediction mode set according to the second prediction directions and the multiple first prediction modes; and performing intra prediction on the current processing block based on the prediction mode set.

Abstract: Chroma intra prediction methods and devices are provided. The method comprises parsing bitstream data corresponding to a current chroma block, and determining that a prediction mode corresponding to the current chroma block is DM; before determining a set of chroma prediction modes based on at least one modified candidate mode, acquiring a linear mode corresponding to the current chroma block; determining an intra prediction mode of the current chroma block from the set of chroma prediction modes, wherein the set of chroma prediction modes comprises at least one of the DM, LM, LM_T or LM_L, wherein when a luma prediction mode corresponding to the DM is one of a DC mode, Planar mode, VER mode or HOR mode, the set of modes comprises an angular mode with an index number 66; and determining a reconstructed value of the current chroma block according to the intra prediction mode.

Abstract: The present application discloses a multi-path resonant circuit and a resonant converter. The multi-path resonant circuit includes at least two parallel N-phase resonant circuits, wherein N is an integer greater than or equal to 3. The at least two parallel N-phase resonant circuits include a first N-phase resonant circuit and a second N-phase resonant circuit. A first resonant inductor in any phase resonant circuit of the first N-phase resonant circuit is coupled with a second resonant inductor in any phase resonant circuit of the second N-phase resonant circuit. In this way, current sharing of the multi-path resonant circuit can be realized through a simpler structure.

Abstract: A battery box and a battery pack are provided. The battery box includes a bottom plate and a side wall. The side wall and the bottom plate enclose a space for accommodating a battery and/or an electrical component. The battery box further includes a lifting column integrally formed with the side wall and a fixed sealing block sleeved on the lifting column. The bottom plate is located between the side wall and the fixed sealing block. The side wall is fixedly connected to the bottom plate through the fixed sealing block. A first sealing member for sealing a gap between the fixed sealing block and the bottom plate is arranged between the fixed sealing block and the bottom plate. The fixed sealing block is sealingly connected to the lifting column.

Abstract: Chroma intra prediction methods and devices are provided. The method comprising: parsing bitstream data corresponding to a current chroma block, and determining that a prediction mode corresponding to the current chroma block is DM; before determining a set of chroma prediction modes based on at least one modified candidate mode, acquiring a linear mode corresponding to the current chroma block from the bitstream data; determining an intra prediction mode of the current chroma block from the set of chroma prediction modes, wherein the set of chroma prediction modes comprises at least one of the DM, LM, LM_T or LM_L, wherein when a luma prediction mode corresponding to the DM is a DC mode or a planar mode, the set of chroma prediction modes comprises a diagonal angular mode with prediction direction index number 66, determining a reconstructed value of the current chroma block according to the intra prediction mode.

Abstract: Chroma intra prediction methods and devices are provided. The method comprises: decoding bitstream data corresponding to a current block, and determining that a prediction mode corresponding to a chroma component of the current block is a direct mode (DM); determining an intra prediction mode of a chroma component of the current block from a set of chroma prediction modes, wherein the set of chroma prediction modes comprises at least one of the DM derived modes, LM, LM_T or LM_L; and determining a reconstructed value of the current chroma block according to the intra prediction mode.

Abstract: The present disclosure discloses a method for processing man-machine dialogues, which includes: acquiring a first user voice message from a client; determining a dialogue intent corresponding to the first user voice message; determining a target duplex wake-up mode corresponding to the dialogue intent based on an intent wake-up mode table, wherein the intent-wake mode table includes duplex wake-up modes corresponding to a plurality of candidate dialogue intents respectively, and the duplex wake-up modes comprise a full-duplex wake-up mode and a half-duplex wake-up mode; and sending a wake-up mode instruction corresponding to the target duplex wake-up mode to the client, such that the client processes the first user voice message according to the target duplex wake-up mode. Using the method and apparatus for carrying out the method, the wake-up mode of the client may be switched dynamically.

Abstract: A method of processing claim data includes: performing word segmentation for each piece of returning description information to obtain at least one claim word; determining at least one material claim word in the claim word; selecting at least one problem description claim word having a description relationship with each material claim word in the claim word; determining the number of association times that each problem description claim word is associated with the corresponding material claim word according to the description relationship between the problem description claim word and the corresponding material claim word; generating uploading verification logic for performing an uploading verification to the claim material according to each material claim word and the corresponding problem description claim word whose number of association times is above a preset threshold; adding the uploading verification logic to claim application page logic.

Abstract: A power battery pack, includes first housing includes a first main portion having a first fixing surface and a first connection surface; a number of first receiving portions extending upwardly from the first fixing surface; a number of first limiting portions extending upwardly from the first connection surface; a second housing comprising a second main portion having a second fixing surface and a second connection surface; a number of second receiving portions extending upwardly from the second fixing surface; a number of second limiting portions extending upwardly from the second connection surface; a number of single batteries; two ends of each single battery being received in a first receiving portion and a respective second receiving portion; two electrode board assemblies respectively received in a first limiting portion; and a number of intermediate board assemblies each received in a first limiting portion or a second limiting portion.

Abstract: A graphics card, a multi-screen display system and a synchronous display method are disclosed. The disclosed method includes the following steps. Firstly, first clock signals are provided in parallel in response to a first clock signal transferred from a motherboard. A second clock signal is generated according to one of the first clock signals that are provided in parallel, wherein the oscillation frequency of the first clock signals is larger than the oscillating frequency of the second clock signal. Then, a set of display clocks are generated based on the second clock signal. The set of display clocks control the display of a set of screens, for synchronous multi-screen display.

Abstract: The present invention provides an image/graphics data display mechanism for continuously displaying image/graphics data on multiple display devices of a computer that contains a system memory directly accessed by the computer's CPU during the CPU's power saving non-responding period, wherein there is provided sufficient system bandwidth, the mechanism of the present invention is independent on the resolution running on each display device and the number of display devices connected to the computer system. The mechanism provides two approaches to achieve continuous display of image/graphics data on multiple display devices computer system. In the first approach, a common clock source is used to coordinate display device horizontal synchronization signals, vertical synchronization signals, horizontal blank periods, and vertical blank periods. In the second approach, the mechanism has a control on the lengths and occurrences of the display device blank periods.

Abstract: An interface unit is described that comprises a buffer for storing captured video data generated by a three dimensional (3D) device intended for a 3D monitor. The interface unit further comprises a synchronization signal extractor configured to extract vertical synchronization (vsync) signals from the video data and a control signal unit configured to derive control signals for a viewing device based on the stored vsync signals. The interface unit transmits the control signals to the viewing device.

Abstract: A graphics card, a multi-screen display system and a synchronous display method are disclosed. The disclosed method includes the following steps. Firstly, first clock signals are provided in parallel in response to a first clock signal transferred from a motherboard. A second clock signal is generated according to one of the first clock signals that are provided in parallel, wherein the oscillation frequency of the first clock signals is larger than the oscillating frequency of the second clock signal. Then, a set of display clocks are generated based on the second clock signal. The set of display clocks control the display of a set of screens, for synchronous multi-screen display.

Abstract: An interface unit is described that comprises a buffer for storing captured video data generated by a three dimensional (3D) device intended for a 3D monitor. The interface unit further comprises a synchronization signal extractor configured to extract vertical synchronization (vsync) signals from the video data and a control signal unit configured to derive control signals for a viewing device based on the stored vsync signals. The interface unit transmits the control signals to the viewing device.

Abstract: The present invention provides an image/graphics data display mechanism for continuously displaying image/graphics data on dual display devices of a computer that contains a Display FIFO and a system memory directly accessed by the computer's CPU, wherein at least one of the display devices is running in a low-resolution mode, the mechanism comprising: determining which of the display devices is running in the low-resolution mode; receiving a power saving signal from the CPU; requesting an access to the system memory, and pre-storing the image/graphics data for the low-resolution device into the Display FIFO; and triggering the CPU power saving process according to a display timing scheme of the other display device.

Abstract: A mechanism is disclosed for adjusting one or more operational parameters of a component in such a way that the adjustment has minimal impact on graphics display. When a component (e.g. a processor) wishes to adjust one or more of its operational parameters (e.g. operating clock frequency), it submits a request to a graphics processing mechanism (GPM). In response, the GPM, which controls multiple displays, sends a response to the component at a proper time to cause the component to adjust the operational parameter during a time period in which a first display and a second display are both experiencing a blank period. By coordinating the timing of the adjustment in this way, it is possible to keep the size of a video memory to a minimum.

Abstract: An uninterrupted data display method for a computer system having a system memory directly accessed by a processor, for preventing disrupted data display from transmission break is disclosed. The method is accomplished before the processor goes into a non-responding period due to an execution of an economical process. The method includes the steps of: (i) providing a data storage device having a depth for storing a period long of data. (ii) Comparing the period of said depth to the non-responding period, if the period of said depth is longer than the non-responding period, jump to step (iii), otherwise, to step (iv). (iii) Loading the period long of data from a system memory into the data storage device then jump to step (v). (iv) Detecting a synchronization pulse then jump to step (v), wherein step (v) is to be accomplished within a non-display period, and, (v) executing the economical process.

Abstract: A mechanism is disclosed for adjusting one or more operational parameters of a component in such a way that the adjustment has minimal impact on graphics display. When a component (e.g. a processor) wishes to adjust one or more of its operational parameters (e.g. operating clock frequency), it submits a request to a graphics processing mechanism (GPM). In response, the GPM, which controls multiple displays, sends a response to the component at a proper time to cause the component to adjust the operational parameter during a time period in which a first display and a second display are both experiencing a blank period. By coordinating the timing of the adjustment in this way, it is possible to keep the size of a video memory to a minimum.

Abstract: The present invention provides an image/graphics data display mechanism for continuously displaying image/graphics data on multiple display devices of a computer that contains a system memory directly accessed by the computer's CPU during the CPU's power saving non-responding period, wherein there is provided sufficient system bandwidth, the mechanism of the present invention is independent on the resolution running on each display device and the number of display devices connected to the computer system. The mechanism provides two approaches to achieve continuous display of image/graphics data on multiple display devices computer system. In the first approach, a common clock source is used to coordinate display device horizontal synchronization signals, vertical synchronization signals, horizontal blank periods, and vertical blank periods. In the second approach, the mechanism has a control on the lengths and occurrences of the display device blank periods.