Abstract: 3D memory devices are disclosed. In an implementation, a 3D memory device includes a stack structure having a core area and a staircase area. The core area includes conductive layers interleaved with first dielectric layers. Each stair of the staircase area has a different number of conductive layers interleaved with a different number of first dielectric layers. The staircase area has contact structures that penetrate through the first surface, a respective one of the stairs, and dielectric material. Each of the contact structures is electrically connected to a contacting conductive layer of the different number of conductive layers of one of the stairs. The staircase area has second dielectric layers, each of which isolates a remainder of the different number of conductive layers of the respective one of the stairs other than the contacting conductive layer from a respective contact structure.

Abstract: A semiconductor device includes a base and a stack structure. The base includes a first surface defining at least one memory plane region. The stack structure is disposed on the first surface, and includes a first portion located at the edge of the memory plane region and a second portion different from the first portion. The first portion includes first contact structures penetrating through the stack structure in a first direction and extending to the base. The second portion includes second contact structures electrically connected with corresponding gate conductor layers in the stack structure. A top surface of the first contact structure away from the base is flush with a top surface of the second contact structure away from the base.