Abstract: A SerDes system is provided. The SerDes system includes channel circuits, a PLL circuit, first and second buffers, and first and second capacitors. Each channel circuit is coupled to the first and second clock lines. The PLL circuit generates a first differential signal including first and second clock signals. The first buffer buffers the first clock signal. The second buffer and buffers the second clock signal. The first capacitor receives the buffered first clock signal and outputs a third clock signal to the first clock line. The second capacitor receives a buffered second clock signal and outputs a fourth clock signal to the second clock line. A swing of a second differential signal comprising the third clock signal and the fourth clock signal is smaller than a swing of the first differential signal.

Abstract: The present invention provides a driving system operating in a first or second modes. The driving system includes first and second resistance adjusting circuits, a divider, a controller and a driver. The divider divides a second resistance adjusting signal generated by the second resistance adjusting circuit by a standard value to generate a first control signal. The controller receives the first control signal and generates a second control signal. When the driving system operates in the first mode, the driver receives the second control signal, according to the second control signal, the driver adjusts an output impedance of itself and adjusts equalization amplitude of a first differential output signal generated by itself. When the driving system operates in the second mode, the driver generates a second differential output signal and adjusts the output impedance according to a first resistance adjusting signal generated by the first resistance adjusting circuit.

Abstract: A SerDes system is provided. The SerDes system includes channel circuits, a PLL circuit, first and second buffers, and first and second capacitors. Each channel circuit is coupled to the first and second clock lines. The PLL circuit generates a first differential signal including first and second clock signals. The first buffer buffers the first clock signal. The second buffer and buffers the second clock signal. The first capacitor receives the buffered first clock signal and outputs a third clock signal to the first clock line. The second capacitor receives a buffered second clock signal and outputs a fourth clock signal to the second clock line. A swing of a second differential signal comprising the third clock signal and the fourth clock signal is smaller than a swing of the first differential signal.