Patents by Inventor Xinyong Wang
Xinyong Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11030382Abstract: A method includes steps of dividing a first arrangement of metal lines in a circuit layout into two sets of metal lines, a first set of metal lines in a peripheral area, and a second set of metal lines in a center area. The arrangement of metal lines is configured to electrically connect to contacts of a second layer of the circuit layout. The method includes adjusting a metal line perimeter of at least one metal line in the center area to make a second arrangement of metal lines, where each adjusted metal line perimeter is separated from contacts in the second layer of the integrated circuit layout by at least a check distance. Metal line material is deposited into a set of openings in a dielectric layer of the integrated circuit, the set of openings corresponding to the second arrangement of metal lines.Type: GrantFiled: October 31, 2019Date of Patent: June 8, 2021Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., TSMC CHINA COMPANY, LIMITEDInventors: XinYong Wang, Li-Chun Tien, Yuan Ma, Qiquan Wang
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Publication number: 20210110000Abstract: A method includes steps of dividing a first arrangement of metal lines in a circuit layout into two sets of metal lines, a first set of metal lines in a peripheral area, and a second set of metal lines in a center area. The arrangement of metal lines is configured to electrically connect to contacts of a second layer of the circuit layout. The method includes adjusting a metal line perimeter of at least one metal line in the center area to make a second arrangement of metal lines, where each adjusted metal line perimeter is separated from contacts in the second layer of the integrated circuit layout by at least a check distance. Metal line material is deposited into a set of openings in a dielectric layer of the integrated circuit, the set of openings corresponding to the second arrangement of metal lines.Type: ApplicationFiled: October 31, 2019Publication date: April 15, 2021Inventors: XinYong WANG, Li-Chun TIEN, Yuan MA, Qiquan WANG
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Publication number: 20200328202Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.Type: ApplicationFiled: June 25, 2020Publication date: October 15, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sheng-Hsiung CHEN, Jerry Chang-Jui KAO, Fong-Yuan CHANG, Po-Hsiang HUANG, Shao-Huan WANG, XinYong WANG, Yi-Kan CHENG, Chun-Chen CHEN
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Patent number: 10741539Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.Type: GrantFiled: November 1, 2017Date of Patent: August 11, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sheng-Hsiung Chen, Jerry Chang-Jui Kao, Fong-Yuan Chang, Po-Hsiang Huang, Shao-Huan Wang, XinYong Wang, Yi-Kan Cheng, Chun-Chen Chen
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Publication number: 20200184138Abstract: A system (including a processor and memory with computer program code) configured to execute a method which includes generating a layout diagram including: generating first and second active area patterns on opposite sides of (and having long axes parallel to) a first symmetry axis; generating non-overlapping first, second and third conductive patterns (having long axes perpendicular to the first symmetry axis) which overlap the first and second active area patterns; centering the first conductive pattern between the second and third conductive patterns; generating a first cut-pattern for, and which overlaps, central regions of the second and third conductive patterns; centering the first cut-pattern relative to the first symmetry axis; generating a fourth conductive pattern over an area bounded by the first cut-pattern; and expanding the fourth conductive pattern to substantially overlap a portion of the first conductive pattern and a portion of the second or third conductive patterns.Type: ApplicationFiled: February 14, 2020Publication date: June 11, 2020Inventors: Li-Chun TIEN, Ting-Wei CHIANG, Shun Li CHEN, Ting Yu CHEN, XinYong WANG
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Patent number: 10565345Abstract: A cell, in a semiconductor device, including: first and second active areas in a semiconductor substrate on opposite sides of the first axis; first, third and fifth, and correspondingly collinear second, fourth and sixth, having long axes in a second direction perpendicular to the first direction; the (A) first, third and fifth, and (B) second, fourth and sixth, conductive structures correspondingly overlapping the second active area; the first and second conductive structures correspondingly being centered between the (C) third and fifth, and (D) fourth and sixth, conductive structures; and a seventh conductive structure; the fourth conductive structure being located over first and second gaps between corresponding ones of the third through sixth, conductive structures; and the fourth conductive structure occupying an area which substantially overlaps one of the first and second conductive structures and a corresponding one of the first and second gaps.Type: GrantFiled: November 30, 2018Date of Patent: February 18, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Li-Chun Tien, Ting-Wei Chiang, Shun Li Chen, Ting Yu Chen, XinYong Wang
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Publication number: 20190303527Abstract: A semiconductor device includes: a conductive layer M(h) including first and second power grid (PG) segments and first routing segments which are conductive, where h is an integer and h?1; long axes of the first and second PG segments and the first routing segments extending in a first direction; the first and second PG segments being separated in a second direction by a PG gap having a midpoint, the second direction being substantially perpendicular to the first direction. The first routing segments are distributed: between the first and second PG segments; and substantially uniformly in the second direction with respect to the midpoint of the PG gap.Type: ApplicationFiled: April 2, 2019Publication date: October 3, 2019Inventors: Li-Chun TIEN, Ting-Wei CHIANG, Shun Li CHEN, Ting Yu CHEN, XinYong WANG
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Patent number: 10339250Abstract: A method of generating an ECO-layout of an ECO base cell includes: generating first and second active area patterns and arranging them on opposite sides of a first axis; generating non-overlapping first, second and third conductive patterns and arranging each of them so as to correspondingly overlap the first and second active area patterns; locating the first conductive pattern between the second and third conductive patterns; generating a first cut-pattern which overlaps corresponding central regions of the second, and third conductive patterns; aligning the first cut-pattern relative to the first axis; generating a fourth conductive pattern; locating the fourth conductive pattern over an area bounded by the first cut-pattern; and expanding the fourth conductive pattern to occupy an area which substantially overlaps a first segment of the first conductive pattern and a first segment of one of the second and third conductive patterns, thereby resulting in the ECO-layout.Type: GrantFiled: March 30, 2017Date of Patent: July 2, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Li-Chun Tien, Ting-Wei Chiang, Shun Li Chen, Ting Yu Chen, XinYong Wang
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Publication number: 20190114382Abstract: A cell, in a semiconductor device, including: first and second active areas in a semiconductor substrate on opposite sides of the first axis; first, third and fifth, and correspondingly collinear second, fourth and sixth, having long axes in a second direction perpendicular to the first direction; the (A) first, third and fifth, and (B) second, fourth and sixth, conductive structures correspondingly overlapping the second active area; the first and second conductive structures correspondingly being centered between the (C) third and fifth, and (D) fourth and sixth, conductive structures; and a seventh conductive structure; the fourth conductive structure being located over first and second gaps between corresponding ones of the third through sixth, conductive structures; and the fourth conductive structure occupying an area which substantially overlaps one of the first and second conductive structures and a corresponding one of the first and second gaps.Type: ApplicationFiled: November 30, 2018Publication date: April 18, 2019Inventors: Li-Chun TIEN, Ting-Wei CHIANG, Shun Li CHEN, Ting Yu CHEN, XinYong WANG
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Patent number: 10231152Abstract: The present invention discloses a network handover method, where after UE in an LTE network requests circuit switched fallback CSFB, an MME instructs an eNB to move the UE from the LTE network to a 2G or 3G network, and requests an MSC to hand over the UE from the LTE network to a CS domain of the 2G or 3G network for the CSFB, so that the 2G or 3G network allocates a CS domain resource to the UE. After handing over to the CS domain, the UE may perform a CS domain call. By using embodiments of the present invention, an access delay is reduced when the UE accesses the CS domain of the 2G or 3G network, duration of an entire voice call is shortened, and user experience is improved.Type: GrantFiled: December 11, 2015Date of Patent: March 12, 2019Assignee: Huawei Technologies Co., Ltd.Inventors: Xiaobo Wu, Hai Liu, Daliang Zhang, Xinyong Wang
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Publication number: 20190064770Abstract: Exemplary embodiments for multiple standard cell libraries are disclosed that include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations have similar functionality as their one or more standard cells but are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for analog circuitry and/or digital circuitry of an electronic device. In an exemplary embodiment, a semiconductor foundry and/or semiconductor technology node can impose one or more electronic design constraints on the placement of the one or more standard cells onto an electronic device design real estate.Type: ApplicationFiled: November 1, 2017Publication date: February 28, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sheng-Hsiung CHEN, Jerry Chang-Jui Kao, Fong-Yuan Chang, Po-Hsiang Huang, Shao-Huan Wang, XinYong Wang, Yi-Kan Cheng, Chun-Chen Chen
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Patent number: 10212634Abstract: A communication method includes: sending, by an MME, a bearer setup request message to an eNodeB, where the bearer setup request message is used to instruct the eNodeB to set up a voice bearer for user equipment; and when the MME receives a bearer setup failure message sent by the eNodeB in response to the bearer setup request message, sending, by the MME, an indication message to the user equipment, where the indication message is used to indicate that a voice over VoIMS of the user equipment is unavailable. When setup of a voice bearer of a VoLTE call fails, the user equipment is notified that a VoLTE is unavailable, so that the user equipment can be prevented from continuing attempting to initiate the VoLTE call and exacerbating cell congestion.Type: GrantFiled: April 14, 2016Date of Patent: February 19, 2019Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Xiaobo Wu, Guangwei Wang, Guobao Xi, Chao Sun, Xinyong Wang
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Publication number: 20180324648Abstract: A network handover method is disclosed, where after UE in an LTE network requests circuit switched fallback CSFB, an MME instructs an eNB to move the UE from the LTE network to a 2G or 3G network, and requests an MSC to hand over the UE from the LTE network to a CS domain of the 2G or 3G network for the CSFB, so that the 2G or 3G network allocates a CS domain resource to the UE. After handing over to the CS domain, the UE may perform a CS domain call. By using embodiments of the present invention, an access delay is reduced when the UE accesses the CS domain of the 2G or 3G network, duration of an entire voice call is shortened, and user experience is improved.Type: ApplicationFiled: June 29, 2018Publication date: November 8, 2018Inventors: Xiaobo Wu, Hai Liu, Daliang Zhang, Xinyong Wang
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Publication number: 20180150586Abstract: A method of generating an ECO-layout of an ECO base cell includes: generating first and second active area patterns and arranging them on opposite sides of a first axis; generating non-overlapping first, second and third conductive patterns and arranging each of them so as to correspondingly overlap the first and second active area patterns; locating the first conductive pattern between the second and third conductive patterns; generating a first cut-pattern which overlaps corresponding central regions of the second, and third conductive patterns; aligning the first cut-pattern relative to the first axis; generating a fourth conductive pattern; locating the fourth conductive pattern over an area bounded by the first cut-pattern; and expanding the fourth conductive pattern to occupy an area which substantially overlaps a first segment of the first conductive pattern and a first segment of one of the second and third conductive patterns, thereby resulting in the ECO-layout.Type: ApplicationFiled: March 30, 2017Publication date: May 31, 2018Inventors: Li-Chun TIEN, Ting-Wei CHIANG, Shun Li CHEN, Ting Yu CHEN, XinYong WANG
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Patent number: 9900807Abstract: The embodiments of the present application discloses a circuit switched fallback method, a UE, an MSC, and an MME. The method includes: sending, by a UE to an MME, a request message for requesting to perform CSFB; receiving, by the UE, a switch command sent by an eNodeB; releasing or holding a default CS call of the UE after the UE switches to the CS domain according to the switch command, where the default CS call is generated by the UE according to the switch command; and by using an MSC, initiating, by the UE, a CS call or receiving a CS call. According to the circuit switched fallback method, the UE, the MSC, and the MME in the embodiments of the present application, circuit switched fallback can be implement in a manner of switching by a UE from a PS domain to a CS domain, and reduce a delay.Type: GrantFiled: December 11, 2015Date of Patent: February 20, 2018Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Xiaobo Wu, Hai Liu, Daliang Zhang, Xinyong Wang, Yaowei Han
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Patent number: 9894582Abstract: The embodiments of the present invention provide a congestion control implementation method and apparatus, where the method includes: determining one or more user equipments for which single radio voice call continuity (SRVCC) offloading needs to be performed; sending an SRVCC offload message to an E-UTRAN NodeB serving the one or more user equipments, so that when triggering an SRVCC handover procedure, the E-UTRAN NodeB switches the one or more user equipments from a Long Term Evolution (LTE) domain to a circuit switched (CS) domain. When the SRVCC handover procedure is completed, the one or more user equipments can be switched from VoLTE user equipments to VoCS user equipments. In this way, LTE cell load can be alleviated and QoS of the one or more user equipments can be guaranteed.Type: GrantFiled: September 2, 2015Date of Patent: February 13, 2018Assignee: Huawei Technologies Co., Ltd.Inventors: Xinyong Wang, Haopeng Zhu, Tao Jiang, Xiaobo Wu, Xiaoji Sun, Wei Tan
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Publication number: 20160242087Abstract: The embodiments of the present invention provide a congestion control implementation method and apparatus, where the method includes: determining one or more user equipments for which single radio voice call continuity (SRVCC) offloading needs to be performed; sending an SRVCC offload message to an E-UTRAN NodeB serving the one or more user equipments, so that when triggering an SRVCC handover procedure, the E-UTRAN NodeB switches the one or more user equipments from a Long Term Evolution (LTE) domain to a circuit switched (CS) domain. When the SRVCC handover procedure is completed, the one or more user equipments can be switched from VoLTE user equipments to VoCS user equipments. In this way, LTE cell load can be alleviated and QoS of the one or more user equipments can be guaranteed.Type: ApplicationFiled: September 2, 2015Publication date: August 18, 2016Inventors: Xinyong Wang, Haopeng Zhu, Tao Jiang, Xiaobo Wu, Xiaoji Sun, Wei Tan
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Publication number: 20160234744Abstract: A communication method includes: sending, by an MME, a bearer setup request message to an eNodeB, where the bearer setup request message is used to instruct the eNodeB to set up a voice bearer for user equipment; and when the MME receives a bearer setup failure message sent by the eNodeB in response to the bearer setup request message, sending, by the MME, an indication message to the user equipment, where the indication message is used to indicate that a voice over VoIMS of the user equipment is unavailable. When setup of a voice bearer of a VoLTE call fails, the user equipment is notified that a VoLTE is unavailable, so that the user equipment can be prevented from continuing attempting to initiate the VoLTE call and exacerbating cell congestion.Type: ApplicationFiled: April 14, 2016Publication date: August 11, 2016Applicant: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Xiaobo WU, Guangwei WANG, Guobao XI, Chao SUN, Xinyong Wang
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Publication number: 20160100338Abstract: The present invention discloses a network handover method, where after UE in an LTE network requests circuit switched fallback CSFB, an MME instructs an eNB to move the UE from the LTE network to a 2G or 3G network, and requests an MSC to hand over the UE from the LTE network to a CS domain of the 2G or 3G network for the CSFB, so that the 2G or 3G network allocates a CS domain resource to the UE. After handing over to the CS domain, the UE may perform a CS domain call. By using embodiments of the present invention, an access delay is reduced when the UE accesses the CS domain of the 2G or 3G network, duration of an entire voice call is shortened, and user experience is improved.Type: ApplicationFiled: December 11, 2015Publication date: April 7, 2016Inventors: Xiaobo Wu, Hai Liu, Daliang Zhang, Xinyong Wang
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Publication number: 20160100337Abstract: The embodiments of the present application discloses a circuit switched fallback method, a UE, an MSC, and an MME. The method includes: sending, by a UE to an MME, a request message for requesting to perform CSFB; receiving, by the UE, a switch command sent by an eNodeB; releasing or holding a default CS call of the UE after the UE switches to the CS domain according to the switch command, where the default CS call is generated by the UE according to the switch command; and by using an MSC, initiating, by the UE, a CS call or receiving a CS call. According to the circuit switched fallback method, the UE, the MSC, and the MME in the embodiments of the present application, circuit switched fallback can be implement in a manner of switching by a UE from a PS domain to a CS domain, and reduce a delay.Type: ApplicationFiled: December 11, 2015Publication date: April 7, 2016Applicant: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Xiaobo WU, Hai LIU, Daliang ZHANG, Xinyong WANG, Yaowei HAN