Abstract: The present disclosure discloses a combined apparatus for experimentation on different storage modes of carbon dioxide, which comprises a displacement device, a storage reaction device and a measuring device, wherein the displacement device comprises a displacement pump, and an intermediate oil-water container and an intermediate carbon dioxide container that are arranged in parallel, the displacement pump is connected to a first end of the parallel connection of the intermediate oil-water container and the intermediate carbon dioxide container, and an inlet end of the storage reaction device is connected to a second end of the parallel connection of the intermediate oil-water container and the intermediate carbon dioxide container; the measuring device comprises a weigher, a first pressure detector, a gas-liquid separator, a gas meter and a mineral analyzer, wherein the first pressure detector is arranged in the intermediate oil-water container, and the gas-liquid separator is connected to the outlet end of

Abstract: The present disclosure discloses a combined apparatus for experimentation on different storage modes of carbon dioxide, which comprises a displacement device, a storage reaction device and a measuring device, wherein the displacement device comprises a displacement pump, and an intermediate oil-water container and an intermediate carbon dioxide container that are arranged in parallel, the displacement pump is connected to a first end of the parallel connection of the intermediate oil-water container and the intermediate carbon dioxide container, and an inlet end of the storage reaction device is connected to a second end of the parallel connection of the intermediate oil-water container and the intermediate carbon dioxide container; the measuring device comprises a weigher, a first pressure detector, a gas-liquid separator, a gas meter and a mineral analyzer, wherein the first pressure detector is arranged in the intermediate oil-water container, and the gas-liquid separator is connected to the outlet end of

Abstract: An electrocardiogram analysis method and apparatus, an electronic device and a storage medium are provided. In the method, at least one electrocardiogram data segment to be analyzed of a target user is input into a first electrocardiogram analysis model for analysis, so as to generate heart disease diagnosis result information of the target user; and optionally, when the heart disease diagnosis result information indicates that the probability of the target user suffering from a specific heart disease is relatively low, that is, when the electrocardiogram data segment to be analyzed is an electrocardiogram that looks relatively normal, whether the target user suffers in a paroxysmal manner from the heart disease is further determined. That is, the probability of the target user having the symptom corresponding to the heart disease in the future is predicted to provide early warning information for a future physical health condition of the target user.

Abstract: An objective of the present application is to provide a road characterization method, comprising: acquiring a target road, wherein the target road comprises one or more road segments; determining one or more atomic lanes corresponding to the road segments according to the road segment attribute information of the road segments; and determining lane association information related to the atomic lanes corresponding to the target road; wherein the one or more atomic lanes and the lane association information are used for characterizing the target road. The method can functionally completely describe objective connections of lanes within a target area, including lane connectivity and lane change feasibility.

Abstract: An objective of the present application is to provide a road characterization method, comprising: acquiring a target road, wherein the target road comprises one or more road segments; determining one or more atomic lanes corresponding to the road segments according to the road segment attribute information of the road segments; and determining lane association information related to the atomic lanes corresponding to the target road; wherein the one or more atomic lanes and the lane association information are used for characterizing the target road. The method can functionally completely describe objective connections of lanes within a target area, including lane connectivity and lane change feasibility.

Abstract: Aspects of the disclosure provide a method for linking input files during a linking process. The method includes receiving an input section that is to be mapped to a memory segment by a linker circuit, determining whether an out-of-memory (OOM) event occurs when an available memory space of the memory segment is unable to accommodate the input section, estimating a memory expansion size that would be required for the memory segment to be able to accommodate the input section when an OOM event occurs, and creating by the linker circuit a map file that includes the estimated memory expansion size of the memory segment.

Abstract: Aspects of the disclosure provide a method for identifying an induction variable in a loop during a compiling process. The method includes searching for a phi-function that includes a first operand and a second operand and defines a candidate basic induction variable (BIV), searching for an add/sub instruction that has a first register and a second register wherein the first register is the second operand of the phi-function, or the value in the first register is subsequently stored to the second operand of the phi-function through one or more move instructions, and determining the candidate BIV is a BIV when the second register of the add/sub instruction is the candidate BIV or stores a value that is passed from the candidate BIV through one or more move instructions.

Abstract: System and methods are provided for register allocation. An original code block and a target code block associated with a branch of an execution loop are determined. An original allocation of a plurality of physical registers to one or more original variables associated with the original code block is detected. A target allocation of the plurality of physical registers to one or more target variables associated with the target code block is determined. One or more temporary registers are selected from the plurality of physical registers based at least in part on the original allocation and the target allocation. The original allocation is changed to the target allocation using the selected temporary registers. Specifically, one or more instructions are generated to change the original allocation to the target allocation using the selected temporary registers. The instructions are executed using one or more processors.

Abstract: Aspects of the disclosure provide a method to support performance analysis. The method includes compiling bytecodes to generate native codes corresponding to the bytecodes in an electronic device, generating a file to include the bytecodes and the corresponding native codes in the file, collecting symbol information to map symbols in the bytecodes with offsets of corresponding native codes, and including the symbol information in the file to enable profiling.

Abstract: Aspects of the disclosure provide a method for code compilation. The method includes receiving instructions of a loop code for compiling, allocating one or more registers to variables before compiling the instructions into a loop body for the loop code, and compiling the instructions into the loop body based on the allocated registers.

Abstract: Aspects of the disclosure provide a method for instruction scheduling. The method includes receiving a sequence of instructions, identifying redundant flag-register based dependency of the instructions, and re-ordering the instructions without being restricted by the redundant flag-register based dependency.

Abstract: System and methods are provided for loop process suspension. One or more loop instructions associated with a loop process are loaded in a code cache. One or more branch instructions associated with a branch of the loop process in the code cache are determined. A suspension event is detected. The branch instructions are replaced with one or more jump instructions in the code cache upon the detection of the suspension event. If the jump instructions are executed in the code cache, the branch instructions in the code cache are restored, and the loop process is suspended. One or more suspension instructions associated with the suspension event are executed in an interpreter.

Abstract: Aspects of the disclosure provide a method to support performance analysis. The method includes compiling bytecodes to generate native codes corresponding to the bytecodes in an electronic device, generating a file to include the bytecodes and the corresponding native codes in the file, collecting symbol information to map symbols in the bytecodes with offsets of corresponding native codes, and including the symbol information in the file to enable profiling.

Abstract: System and methods are provided for loop process suspension. One or more loop instructions associated with a loop process are loaded in a code cache. One or more branch instructions associated with a branch of the loop process in the code cache are determined. A suspension event is detected. The branch instructions are replaced with one or more jump instructions in the code cache upon the detection of the suspension event. If the jump instructions are executed in the code cache, the branch instructions in the code cache are restored, and the loop process is suspended. One or more suspension instructions associated with the suspension event are executed in an interpreter.

Abstract: System and methods are provided for register allocation. An original code block and a target code block associated with a branch of an execution loop are determined. An original allocation of a plurality of physical registers to one or more original variables associated with the original code block is detected. A target allocation of the plurality of physical registers to one or more target variables associated with the target code block is determined. One or more temporary registers are selected from the plurality of physical registers based at least in part on the original allocation and the target allocation. The original allocation is changed to the target allocation using the selected temporary registers. Specifically, one or more instructions are generated to change the original allocation to the target allocation using the selected temporary registers. The instructions are executed using one or more processors.

Abstract: Aspects of the disclosure provide a method for instruction scheduling. The method includes receiving a sequence of instructions, identifying redundant flag-register based dependency of the instructions, and re-ordering the instructions without being restricted by the redundant flag-register based dependency.

Abstract: Aspects of the disclosure provide a method for code compilation. The method includes receiving instructions of a loop code for compiling, allocating one or more registers to variables before compiling the instructions into a loop body for the loop code, and compiling the instructions into the loop body based on the allocated registers.