Patents by Inventor Xiong Fang

Xiong Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11400083
    Abstract: The present invention provides a compound represented by formula (I), or a pharmaceutically acceptable salt or prodrug thereof.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: August 2, 2022
    Assignee: TSINGHUA UNIVERSITY
    Inventors: Ziwei Huang, Xiong Fang, Qian Meng, Yan Xu, Siyu Zhu, Xiao Fang
  • Patent number: 11349704
    Abstract: An illustrative embodiment of a disclosed physical layer interface device includes: a first transmitter and a first receiver for a primary data path; a second transmitter and a second receiver for a secondary data path; a third transmitter and a third receiver for a non-redundant data path; and a multiplexer. The third receiver is coupled to provide a data stream received from the non-redundant data path concurrently to the first and second transmitters, and the multiplexer provides the third transmitter with a selected one of the data stream received via the primary data path and the data stream received via the secondary data path. Disclosed network switch embodiments employ the illustrative physical layer interface to provide internal or external data path redundancy for traffic handled by the network switch.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: May 31, 2022
    Assignee: Credo Technology Group Limited
    Inventors: Calvin Xiong Fang, Haoli Qian, Ashwin Upadhya
  • Publication number: 20220021603
    Abstract: Active Ethernet cables that provide data path redundancy. One illustrative cable embodiment includes a first connector connected to each of a second and third connectors, the first connector including a multiplexer that couples a data stream from a selectable one of the second and third connectors to an output of the first connector. One illustrative method embodiment includes: producing from an output of a first connector a data stream from a currently selected one of multiple redundant connectors; monitoring the data stream for a fault associated with the currently selected one of multiple redundant connectors; and responsive to detecting said fault, producing from the output of the first connector a data stream from a different selected one of the multiple redundant connectors.
    Type: Application
    Filed: July 20, 2020
    Publication date: January 20, 2022
    Applicant: Credo Technology Group Limited
    Inventors: Haoli Qian, Calvin Xiong Fang, William Brennan, Jeffrey Twombly
  • Publication number: 20210399941
    Abstract: An illustrative embodiment of a disclosed physical layer interface device includes: a first transmitter and a first receiver for a primary data path; a second transmitter and a second receiver for a secondary data path; a third transmitter and a third receiver for a non-redundant data path; and a multiplexer. The third receiver is coupled to provide a data stream received from the non-redundant data path concurrently to the first and second transmitters, and the multiplexer provides the third transmitter with a selected one of the data stream received via the primary data path and the data stream received via the secondary data path. Disclosed network switch embodiments employ the illustrative physical layer interface to provide internal or external data path redundancy for traffic handled by the network switch.
    Type: Application
    Filed: June 17, 2020
    Publication date: December 23, 2021
    Applicant: Credo Technology Group Limited
    Inventors: Calvin Xiong Fang, Haoli Qian, Ashwin Upadhya
  • Patent number: 11199584
    Abstract: Accordingly, an improved interposer connection testing technique is provided, employing parallel pseudo-random bit sequence (PRBS) generators to test all the interconnects in parallel and simultaneously detect any correctable defects. In one embodiment, a microelectronic assembly includes an interposer electrically connected in a flip-chip configuration to an originating IC (integrated circuit) die and to a destination IC die, the substrate having multiple conductive traces for a parallel communications bus between the IC dies. The originating IC die has a first parallel PRBS (pseudo-random binary sequence) generator to drive test PRBSs with different phases in parallel across the interposer traces. The destination IC die has a second parallel PRBS generator to create reference PRBSs with different phases, and a bitwise comparator coupled to receive the test PRBSs from the interposer traces and to compare them to the reference PRBSs to provide concurrent fault monitoring for each of the traces.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: December 14, 2021
    Assignee: Credo Technology Group Limited
    Inventor: Calvin Xiong Fang
  • Publication number: 20200379044
    Abstract: Accordingly, an improved interposer connection testing technique is provided, employing parallel pseudo-random bit sequence (PRBS) generators to test all the interconnects in parallel and simultaneously detect any correctable defects. In one embodiment, a microelectronic assembly includes an interposer electrically connected in a flip-chip configuration to an originating IC (integrated circuit) die and to a destination IC die, the substrate having multiple conductive traces for a parallel communications bus between the IC dies. The originating IC die has a first parallel PRBS (pseudo-random binary sequence) generator to drive test PRBSs with different phases in parallel across the interposer traces. The destination IC die has a second parallel PRBS generator to create reference PRBSs with different phases, and a bitwise comparator coupled to receive the test PRBSs from the interposer traces and to compare them to the reference PRBSs to provide concurrent fault monitoring for each of the traces.
    Type: Application
    Filed: January 17, 2018
    Publication date: December 3, 2020
    Applicant: Credo Technology Group Limited
    Inventor: Calvin Xiong FANG
  • Publication number: 20200268729
    Abstract: The present invention provides a compound represented by formula (I), or a pharmaceutically acceptable salt or prodrug thereof.
    Type: Application
    Filed: December 1, 2017
    Publication date: August 27, 2020
    Inventors: Ziwei HUANG, Xiong FANG, Qian MENG, Yan XU, Siyu ZHU, Xiao FANG
  • Patent number: 9484838
    Abstract: An inverter and a power supply method thereof and an application thereof are provided. The inverter includes a DC-DC conversion circuit, an inverting circuit and an auxiliary power circuit. The DC-DC conversion circuit converts a DC input voltage into a DC bus voltage. The inverting circuit is configured to convert the DC bus voltage into an AC output voltage. The auxiliary power circuit is enabled in response to the DC input voltage, and the auxiliary power circuit generates a first auxiliary power for enabling the DC-DC conversion circuit after being enabled. The DC-DC conversion circuit is enabled in response to the first auxiliary power, and the DC-DC conversion circuit generates a second auxiliary power for enabling the inverting circuit after being enabled, such that the inverting circuit is enabled in response to the second auxiliary power and generates the AC output voltage.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: November 1, 2016
    Assignees: FSP-Powerland Technology Inc., FSP TECHNOLOGY INC.
    Inventors: Jian-Guo Mu, Feng Ji, Xiong Fang, Chuan-Yun Wang, Ming Xu
  • Patent number: 9246604
    Abstract: Systems, methods, and other embodiments associated with echo cancellation are described. According to one embodiment, an apparatus includes a cable tester that determines whether a fault in a cable exists by using echo cancellation values.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: January 26, 2016
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Junqing Sun, Danjin Wu, Xiong Fang, Baohua Chen, William Lo
  • Publication number: 20150049525
    Abstract: An inverter and a power supply method thereof and an application thereof are provided. The inverter includes a DC-DC conversion circuit, an inverting circuit and an auxiliary power circuit. The DC-DC conversion circuit converts a DC input voltage into a DC bus voltage. The inverting circuit is configured to convert the DC bus voltage into an AC output voltage. The auxiliary power circuit is enabled in response to the DC input voltage, and the auxiliary power circuit generates a first auxiliary power for enabling the DC-DC conversion circuit after being enabled. The DC-DC conversion circuit is enabled in response to the first auxiliary power, and the DC-DC conversion circuit generates a second auxiliary power for enabling the inverting circuit after being enabled, such that the inverting circuit is enabled in response to the second auxiliary power and generates the AC output voltage.
    Type: Application
    Filed: July 14, 2014
    Publication date: February 19, 2015
    Inventors: Jian-Guo Mu, Feng Ji, Xiong Fang, Chuan-Yun Wang, Ming Xu
  • Patent number: 8582443
    Abstract: Systems, methods, and other embodiments associated with echo cancellation are described. According to one embodiment, an apparatus includes a cable tester that determines whether a fault in a cable exists by using echo cancellation values.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: November 12, 2013
    Assignee: Marvell International Ltd.
    Inventors: Junqing Sun, Danjin Wu, Xiong Fang, Baohua Chen, William Lo