Patents by Inventor Xiongfei Yu

Xiongfei Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12163174
    Abstract: A method for producing sclareol by fermentation of cigar tobacco flower buds is provided, including: mixing cigar tobacco flower buds with deionized water, sterilizing and adding edible yeast, then fermenting at 25-30° C. and 100-300 rpm/min for 24-30 h. This method uses cigar tobacco flower buds as the sole raw material, without adding additional nutrients, and only ferments tobacco flower buds with edible yeast to synthesize sclareol. Meanwhile, this method has extremely high synthesis efficiency.
    Type: Grant
    Filed: May 13, 2024
    Date of Patent: December 10, 2024
    Assignees: Tobacco Research Institute of Hubei Province, Hubei University of Technology
    Inventors: Jun Yu, Chunlei Yang, Zhi Wang, Xiong Chen, Zongping Li, Jinpeng Yang, Hao Li, Lan Yao, Xiongfei Rao, Hao Peng, Shiping Xu, Wenming Wang
  • Publication number: 20240392325
    Abstract: A method for producing sclareol by fermentation of cigar tobacco flower buds is provided, including: mixing cigar tobacco flower buds with deionized water, sterilizing and adding edible yeast, then fermenting at 25-30° C. and 100-300 rpm/min for 24-30 h. This method uses cigar tobacco flower buds as the sole raw material, without adding additional nutrients, and only ferments tobacco flower buds with edible yeast to synthesize sclareol. Meanwhile, this method has extremely high synthesis efficiency.
    Type: Application
    Filed: May 13, 2024
    Publication date: November 28, 2024
    Inventors: JUN YU, CHUNLEI YANG, ZHI WANG, XIONG CHEN, ZONGPING LI, JINPENG YANG, HAO LI, LAN YAO, XIONGFEI RAO, HAO PENG, SHIPING XU, WENMING WANG
  • Publication number: 20240353304
    Abstract: The present disclosure relates to a method and a device for predicting ability of a temporary plugging agent to plug cracks and a storage medium, and includes the following steps: calculating a plane elastic modulus of a core through experiments, acquiring a maximum force load of a specimen, calculating rock fracture toughness through the maximum force load, manufacturing an artificial crack model and placing it in a core holder, preparing temporary plugging deflection fluid by selecting a temporary plugging agent, injecting the temporary plugging deflection fluid into the artificial crack so as to calculate apparent fracture toughness of the temporarily plugged crack, and finally calculating a fracture pressure of the temporarily plugged crack based on the calculated rock fracture toughness and the plane elastic modulus of the core. Through the above method, the present disclosure provides a standard fracture pressure calculation method.
    Type: Application
    Filed: April 19, 2024
    Publication date: October 24, 2024
    Inventors: Daobing Wang, Bo Yu, Haiyan Zhu, Fujian Zhou, Dongliang Sun, Xiongfei Liu, Tiankui Guo, Xiuhui Li, Xuanhe Tang, Xian Shi, Qing Liu, Yu Suo, Yang Shi
  • Patent number: 8188550
    Abstract: A method of forming an IC is presented. The method includes providing a substrate having a plurality of transistors formed thereon. The transistors have gate stack, source and drain regions. An electrical strap is formed and in contact with at least a portion of at least one sidewall of the gate stack of a first transistor to provide a continuous electrical flowpath over a gate electrode of the first transistor and the source or drain region of a second transistor.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: May 29, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Lieyong Yang, Siau Ben Chiah, Ming Lei, Hua Xiao, Xiongfei Yu, Kelvin Tianpeng Guan, Puay San Chia, Chor Shu Cheng, Gary Chia, Chee Kong Leong, Sean Lian, Kin San Pey, Chao Yong Li
  • Publication number: 20090166758
    Abstract: A method of forming an IC is presented. The method includes providing a substrate having a plurality of transistors formed thereon. The transistors have gate stack, source and drain regions. An electrical strap is formed and in contact with at least a portion of at least one sidewall of the gate stack of a first transistor to provide a continuous electrical flowpath over a gate electrode of the first transistor and the source or drain region of a second transistor.
    Type: Application
    Filed: September 30, 2008
    Publication date: July 2, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Lieyong YANG, Siau Ben CHIAH, Ming LEI, Hua XIAO, Xiongfei YU, Kelvin Tianpeng GUAN, Puay San CHIA, Chor Shu CHENG, Gary CHIA, Chee Kong LEONG, Sean LIAN, Kin San PEY, Chao Yong LI