Abstract: A blockchain-based interaction method and system for an edge computing service: using, as a bearing entity of an MECaaS, a device that has an environment for an operating system and that is of a user; registering a computing power device of the user as an edge node by using the MECaaS; uploading or updating registration information of the edge node to a blockchain layer; issuing, by a requesting device as a data producer, a computing task to the MECaaS; invoking, by the MECaaS, the smart contract deployed on the blockchain layer; standardizing a data format of the computing task; matching a target edge node for the requesting device; establishing an M2M communication between the requesting device and the target edge node, so that the requesting device can transmit raw data to the target edge node, and the target edge node can feed back a computing result to the requesting device.

Abstract: A gate driver circuit, a display device and a driving method. The gate driver circuit includes: a scan signal generation circuit, wherein the scan signal generation circuit includes N1 stages of first output terminals, and the scan signal generation circuit is configured to output N1 first pulse scan signals stage by stage respectively through the N1 stages of first output terminals; and N2 level conversion circuits, wherein the N2 level conversion circuits are configured to output under a control of a plurality of conversion control signals N1 second pulse scan signals which are in one-to-one correspondence with the N1 first pulse scan signals, and the plurality of conversion control signals include a plurality of first sub-control signals which are the N1 first pulse scan signals, wherein N1 is an integer greater than or equal to 2, and N2 is an integer greater than or equal to 2.

Abstract: A gate driving unit circuit comprises an input sub-circuit and an output sub-circuit. The input sub-circuit is connected to a first pull-up node, a second pull-up node, and an input terminal, and transmits a signal input from the input terminal to the first pull-up node and the second pull-up node. The output sub-circuit is connected to the first pull-up node, the second pull-up node, a first control terminal, a third control terminal, a first output terminal, and a second output terminal. The output sub-circuit transmits a signal input through the first control terminal to the first output terminal, and transmits a signal input through the third control terminal to the second output terminal under the control of a potential of the second pull-up node, wherein, an effective voltage of a signal of the first control terminal is greater than that of a signal of the third control terminal.

Abstract: A shift register unit, a gate drive circuit, a display device and a method of driving a gate drive circuit are provided. The shift register unit includes a shift register circuit and an output control circuit. The shift register circuit is configured to output a valid output level at a first output terminal according to a first input signal received by a first input terminal, and is configured to reset according to a first reset signal received by a first reset terminal. The output control circuit is configured to output an invalid output level at the second output terminal according to a second input signal received by the second input terminal, thereby controlling a level of the first output terminal to the invalid output level, and is configured to reset according to a second reset signal received by the second reset terminal.

Abstract: A shift register circuit includes a pull-up control sub-circuit, a pull-up sub-circuit and a shutdown auxiliary sub-circuit. The pull-up control sub-circuit is configured to transmit a voltage from the signal input terminal to the pull-up node under the control of the voltage from the signal input terminal. The shut-down auxiliary sub-circuit is configured to pull down a voltage of the pull-up node to a voltage of the discharge voltage terminal under the control of a voltage from the pull-up node. The pull-up sub-circuit is configured to transmit a voltage from the clock signal terminal to the first signal output terminal under the control of a voltage from the pull-up node. The first signal output terminal is configured to be connected to a gate line.

Abstract: The present application provides a GOA circuit, a GOA circuit driving method, a GOA driving circuit and a display device, the GOA circuit includes: a front-end GOA circuit, which is connected to a connection signal input terminal, a reset signal terminal, a first power supply voltage terminal, and a second power supply voltage terminal, a third power supply voltage terminal, a clock signal terminal, and a front-end output terminal, and is configured to output a clock signal at the clock signal terminal to the front-end output terminal when an input signal at the signal input terminal is at an active input level; and a repair circuit, which is connected to the front-end output terminal, a frame start signal, the first power supply voltage terminal, and an output terminal of the GOA circuit.

Abstract: A gate driver circuit, a display device and a driving method. The gate driver circuit includes: a scan signal generation circuit, wherein the scan signal generation circuit includes N1 stages of first output terminals, and the scan signal generation circuit is configured to output N1 first pulse scan signals stage by stage respectively through the N1 stages of first output terminals; and N2 level conversion circuits, wherein the N2 level conversion circuits are configured to output under a control of a plurality of conversion control signals N1 second pulse scan signals which are in one-to-one correspondence with the N1 first pulse scan signals, and the plurality of conversion control signals include a plurality of first sub-control signals which are the N1 first pulse scan signals, wherein N1 is an integer greater than or equal to 2, and N2 is an integer greater than or equal to 2.

Abstract: A gate driving unit circuit comprises an input sub-circuit and an output sub-circuit. The input sub-circuit is connected to a first pull-up node, a second pull-up node, and an input terminal, and transmits a signal input from the input terminal to the first pull-up node and the second pull-up node. The output sub-circuit is connected to the first pull-up node, the second pull-up node, a first control terminal, a third control terminal, a first output terminal, and a second output terminal. The output sub-circuit transmits a signal input through the first control terminal to the first output terminal, and transmits a signal input through the third control terminal to the second output terminal under the control of a potential of the second pull-up node, wherein, an effective voltage of a signal of the first control terminal is greater than that of a signal of the third control terminal.

Abstract: A shift register unit, a gate drive circuit, a display device and a method of driving a gate drive circuit are provided. The shift register unit includes a shift register circuit and an output control circuit. The shift register circuit is configured to output a valid output level at a first output terminal according to a first input signal received by a first input terminal, and is configured to reset according to a first reset signal received by a first reset terminal. The output control circuit is configured to output an invalid output level at the second output terminal according to a second input signal received by the second input terminal, thereby controlling a level of the first output terminal to the invalid output level, and is configured to reset according to a second reset signal received by the second reset terminal.

Abstract: The present application provides a GOA circuit, a GOA circuit driving method, a GOA driving circuit and a display device, the GOA circuit includes: a front-end GOA circuit, which is connected to a connection signal input terminal, a reset signal terminal, a first power supply voltage terminal, and a second power supply voltage terminal, a third power supply voltage terminal, a clock signal terminal, and a front-end output terminal, and is configured to output a clock signal at the clock signal terminal to the front-end output terminal when an input signal at the signal input terminal is at an active input level; and a repair circuit, which is connected to the front-end output terminal, a frame start signal, the first power supply voltage terminal, and an output terminal of the GOA circuit.

Abstract: A shift register unit is provided, which includes an input circuit, a first output circuit and a first output signal adjustment circuit. The input circuit is configured for receiving an input signal from an input terminal and controlling an electrical signal of a first node based on the input signal. The first output circuit is configured for outputting a first output signal at a first output terminal of the shift register unit based on a first clock signal under control of the electrical signal of the first node. The first output signal adjustment circuit is configured for providing a first reference signal to the first output terminal under control of the second clock signal so as to decrease an amplitude of the first output signal.

Abstract: A gate drive circuit, a display device and a driving method are provided. The gate drive circuit includes a scan signal generation circuit and output control circuits in N stages. The scan signal generation circuit includes first output terminals in 2N stages, and is configured to output scan pulse signals in an order at the first output terminals in 2N stages; each of the output control circuits in N stages includes an input terminal, a first control terminal, a second control terminal, a second output terminal, and a bootstrap circuit, and is configured to control the bootstrap circuit, under control of a first control signal received by the first control terminal, an input signal received by the input terminal, and a second control signal received by the second control terminal, to output an output pulse signal with different pulse levels at the second output terminal.

Abstract: The present disclosure provides a display substrate, a method for preparing the same, and a display motherboard. The display substrate comprises: a plurality of display areas spaced apart from each other, each of which is provided with a plurality of spacers; and a blank area between any two adjacent display areas of the plurality of display areas, and provided with a plurality of supporters having the same material and height as the spacers. Since the blank area is provided with the supporters in the display substrate of this disclosure, the problem with uneven cell gap between the blank area and the display area under an action of atmospheric pressure is effectively avoided, thereby preventing the phenomenon that the display motherboard at a place with a greater cell gap presents a yellow color when displaying.

Abstract: A gate drive circuit, a display device and a driving method are provided. The gate drive circuit includes a scan signal generation circuit and output control circuits in N stages. The scan signal generation circuit includes first output terminals in 2N stages, and is configured to output scan pulse signals in an order at the first output terminals in 2N stages; each of the output control circuits in N stages includes an input terminal, a first control terminal, a second control terminal, a second output terminal, and a bootstrap circuit, and is configured to control the bootstrap circuit, under control of a first control signal received by the first control terminal, an input signal received by the input terminal, and a second control signal received by the second control terminal, to output an output pulse signal with different pulse levels at the second output terminal.

Abstract: There are provided a shift register unit and a driving method thereof. The shift register unit includes: an input circuit, whose first terminal receives an input signal of the shift register unit, and second terminal is connected to a pull-up node, the input circuit being configured to output the input signal to the pull-up node; an output circuit, whose first terminal is connected to a clock signal terminal, second terminal is connected to the pull-up node, third terminal is connected to an output terminal of the shift register unit, the output circuit being configured to output a signal of the clock signal terminal to the output terminal under the control of the pull-up node; a pull-up node control circuit, and the pull-up node control circuit being configured to discharge the pull-up node through third power supply voltage terminal under the control of a first power supply voltage terminal.

Abstract: A gate drive circuit, a display device and a driving method are provided. The gate drive circuit includes a scan signal generation circuit and output control circuits in N stages. The scan signal generation circuit includes first output terminals in 2N stages, and is configured to output scan pulse signals in an order at the first output terminals in 2N stages; each of the output control circuits in N stages includes an input terminal, a first control terminal, a second control terminal, a second output terminal, and a bootstrap circuit, and is configured to control the bootstrap circuit, under control of a first control signal received by the first control terminal, an input signal received by the input terminal, and a second control signal received by the second control terminal, to output an output pulse signal with different pulse levels at the second output terminal.

Abstract: A polarizer, a polarizer, a color film substrate, a display panel, and a method of conducting away electrostatic charges are disclosed. The polarizer includes a transparent conductive film layer where the transparent conductive film layer is added with a conductive material, and when the polarizer comprising the transparent conductive film layer connects to a ground, the conductive material that is added to the transparent conductive film layer enables the polarizer to conduct electrostatic charges away from the polarizer to the ground.

Abstract: Disclosed is a pixel driving circuit, comprising a driving control circuit, a first driving circuit and a second driving circuit. The driving control circuit is configured to control one of the first driving circuit and the second driving circuit to be turned on under the condition the first scanning line outputs an effective voltage signal, and control the other of the first driving circuit and the second driving circuit to be turned on under the condition the second scanning line outputs an effective voltage signal. The first driving circuit is configured to drive the light emitting circuit to emit light under control of the driving control circuit. The second driving circuit is configured to drive the light emitting circuit to emit light under control of the driving control circuit.

Abstract: The present disclosure provides an aluminum alloy casing, a preparation method thereof, and a personal electronic device. The aluminum alloy casing includes an aluminum alloy matrix and an oxide film layer covering the surface of the aluminum alloy matrix, wherein the aluminum alloy matrix has a slit, the oxide film layer includes an inner anodic oxide film layer and an outer anodic oxide film layer, and the inner anodic oxide film layer has inner anodic oxide film layer nanopores; and the outer anodic oxide film layer has outer anodic oxide film layer nanopores.

Abstract: A shift register unit is provided, which includes an input circuit, a first output circuit and a first output signal adjustment circuit. The input circuit is configured for receiving an input signal from an input terminal and controlling an electrical signal of a first node based on the input signal. The first output circuit is configured for outputting a first output signal at a first output terminal of the shift register unit based on a first clock signal under control of the electrical signal of the first node. The first output signal adjustment circuit is configured for providing a first reference signal to the first output terminal under control of the second clock signal so as to decrease an amplitude of the first output signal.