Patents by Inventor Xiongfei MENG

Xiongfei MENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MULTI POWER DOMAINS TO REDUCE OCV USING CPR INFRASTRUCTURE
    Publication number: 20180173288
    Abstract: According to certain aspects, a system includes frequency measurement devices distributed across a power domain on a chip, wherein the power domain is divided into multiple power sub-domains, and each of the power sub-domains includes a respective subset of the frequency measurement devices. The system also includes a power manager. For each of the power sub-domains, the power manager is configured to receive frequency measurements from the respective subset of the frequency measurement devices, and determine a supply voltage setting for the power sub-domain based on the received frequency measurements from the respective subset of the frequency measurement devices.
    Type: Application
    Filed: December 20, 2016
    Publication date: June 21, 2018
    Inventors: Xiongfei Meng, Pranjal Srivastava, Patrick Drennan
  • Via structure for optimizing signal porosity
    Patent number: 9620452
    Abstract: An apparatus including a conductive stack structure includes an Mx layer interconnect on an Mx layer and extending in a first direction on a first track, an My layer interconnect on an My layer in which the My layer is a lower layer than the Mx layer, a first via stack coupled between the Mx layer interconnect and the My layer interconnect, a second via stack coupled between the Mx layer interconnect and the My layer interconnect, a second Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mx layer interconnect is between the second Mx layer interconnect and the third Mx layer interconnect. The second Mx layer interconnect and the third Mx layer interconnect are uncoupled to each other.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: April 11, 2017
    Assignee: QUALCOMM INCORPORATED
    Inventors: Xiongfei Meng, Joon Hyung Chung, Yuancheng Christopher Pan
  • VIA STRUCTURE FOR OPTIMIZING SIGNAL POROSITY
    Publication number: 20170053866
    Abstract: An apparatus including a conductive stack structure includes an Mx layer interconnect on an Mx layer and extending in a first direction on a first track, an My layer interconnect on an My layer in which the My layer is a lower layer than the Mx layer, a first via stack coupled between the Mx layer interconnect and the My layer interconnect, a second via stack coupled between the Mx layer interconnect and the My layer interconnect, a second Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mx layer interconnect is between the second Mx layer interconnect and the third Mx layer interconnect. The second Mx layer interconnect and the third Mx layer interconnect are uncoupled to each other.
    Type: Application
    Filed: November 8, 2016
    Publication date: February 23, 2017
    Inventors: Xiongfei MENG, Joon Hyung CHUNG, Yuancheng Christopher PAN
  • Via structure for optimizing signal porosity
    Patent number: 9520358
    Abstract: An apparatus including a conductive stack structure includes an Mx layer interconnect on an Mx layer and extending in a first direction on a first track, an My layer interconnect on an My layer in which the My layer is a lower layer than the Mx layer, a first via stack coupled between the Mx layer interconnect and the My layer interconnect, a second via stack coupled between the Mx layer interconnect and the My layer interconnect, a second Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mx layer interconnect is between the second Mx layer interconnect and the third Mx layer interconnect. The second Mx layer interconnect and the third Mx layer interconnect are uncoupled to each other.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: December 13, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Xiongfei Meng, Joon Hyung Chung, Yuancheng Christopher Pan
  • VIA STRUCTURE FOR OPTIMIZING SIGNAL POROSITY
    Publication number: 20160126180
    Abstract: An apparatus including a conductive stack structure includes an Mx layer interconnect on an Mx layer and extending in a first direction on a first track, an My layer interconnect on an My layer in which the My layer is a lower layer than the Mx layer, a first via stack coupled between the Mx layer interconnect and the My layer interconnect, a second via stack coupled between the Mx layer interconnect and the My layer interconnect, a second Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mx layer interconnect is between the second Mx layer interconnect and the third Mx layer interconnect. The second Mx layer interconnect and the third Mx layer interconnect are uncoupled to each other.
    Type: Application
    Filed: June 19, 2015
    Publication date: May 5, 2016
    Inventors: Xiongfei MENG, Joon Hyung CHUNG, Yuancheng Christopher PAN