Abstract: A computer device and a method for reading or writing data by a computer device are provided. In the computer device, a central processing unit (CPU) is connected to a cloud controller using a double data rate (DDR) interface. Because the DDR interface has a high data transmission rate, interruption of CPU can be avoided. In addition, the CPU converts a read or write operation request into a control command and writes the control command into a transmission queue in the cloud controller. Because the cloud controller performs a read operation or a write operation on a network device according to operation information in the control command, after writing the control command into the transmission queue, the CPU does not need to wait for an operation performed by the cloud controller and can continue to perform other processes.

Abstract: A translation lookaside buffer (TLB) management method and a multi-core processor are provided. The method includes: receiving, by a first core, a first address translation request; querying a TLB of the first core based on the first address translation request; determining that a first target TLB entry corresponding to the first address translation request is missing in the TLB of the first core, obtaining the first target TLB entry; determining that entry storage in the TLB of the first core is full; determining a second core from cores in an idle state in the multi-core processor; replacing a first entry in the TLB of the first core with the first target TLB entry; storing the first entry in a TLB of the second core. Accordingly, a TLB miss rate is reduced and program execution is accelerated.

Abstract: A method for accessing an entry in a translation lookaside buffer and a processing chip are provided. In the method, the entry includes at least one combination entry, and the combination entry includes a virtual huge page number, a bit vector field, and a physical huge page number. The physical huge page number is an identifier of N consecutive physical pages corresponding to the N consecutive virtual pages. One entry is used to represent a plurality of virtual-to-physical page mappings, so that when a page table length is fixed, a quantity of entries in the TLB can be increased exponentially, thereby increasing a TLB hit probability, and reducing TLB misses. In this way, a delay in program processing can be reduced, and processing efficiency of the processing chip can be improved.

Abstract: A method for accessing an entry in a translation lookaside buffer and a processing chip are provided. In the method, the entry includes at least one combination entry, and the combination entry includes a virtual huge page number, a bit vector field, and a physical huge page number. The physical huge page number is an identifier of N consecutive physical pages corresponding to the N consecutive virtual pages. One entry is used to represent a plurality of virtual-to-physical page mappings, so that when a page table length is fixed, a quantity of entries in the TLB can be increased exponentially, thereby increasing a TLB hit probability, and reducing TLB misses. In this way, a delay in program processing can be reduced, and processing efficiency of the processing chip can be improved.

Abstract: A translation lookaside buffer (TLB) management method and a multi-core processor are provided. the method includes: receiving, by a first core, a first address translation request; querying a TLB of the first core based on the first address translation request; determining that a first target TLB entry corresponding to the first address translation request is missing in the TLB of the first core, obtaining the first target TLB entry; determining that entry storage in the TLB of the first core is full; determining a second core from cores in an idle state in the multi-core processor; replacing a first entry in the TLB of the first core with the first target TLB entry; storing the first entry in a TLB of the second core. Thereby reducing a TLB miss rate and accelerating program execution.

Abstract: A multiple chip multiprocessor cache coherence operation method and a multiple chip multiprocessor are disclosed. The method includes: receiving a write request for a first data block; finding, in an on-chip directory of the first processor chip, an on-chip directory entry corresponding to the first data block based on an identifier of the first data block, determining, from the found on-chip directory entry, a core identifier of a processor core storing the first data block, sending, to the processor core corresponding to the core identifier, an instruction message for deleting the first data block, skipping sending an inter-chip directory query request for the first data block, and instructing the first processor core to write the to-be-written data into a private cache of the first processor core.

Abstract: A computer device and a method for reading or writing data by a computer device are provided. In the computer device, a central processing unit (CPU) is connected to a cloud controller using a double data rate (DDR) interface. Because the DDR interface has a high data transmission rate, interruption of CPU can be avoided. In addition, the CPU converts a read or write operation request into a control command and writes the control command into a transmission queue in the cloud controller. Because the cloud controller performs a read operation or a write operation on a network device according to operation information in the control command, after writing the control command into the transmission queue, the CPU does not need to wait for an operation performed by the cloud controller and can continue to perform other processes.

Abstract: Embodiments of the present disclosure disclose a method for combining entries, including: determining N to-be-combined entries, where a cache block indicated by an entry label of each entry of the N entries belongs to a combination range, and the combination range indicates 2a cache blocks; and combining the N entries into a first entry, where an entry label of the first entry indicates the 2a cache blocks, and a sharer number of the first entry includes a sharer number of each entry of the N entries. According to the method, entries in a directory can be combined effectively, thereby improving directory usage efficiency.

Abstract: The present disclosure discloses a method for accessing a data visitor directory in a multi-core system, a directory cache device, a multi-core system, and a directory storage unit. The method includes: receiving a first access request sent by a first processor core, where the first access request is used to access an entry, corresponding to a first data block, in a directory; determining, according to the first access request, that a single-pointer entry array has a first single-pointer entry corresponding to the first data block; when determining, according to the first single-pointer entry, that a sharing entry array has a first sharing entry associated with the first single-pointer entry, determining multiple visitors of the first data block according to the first sharing entry. According to embodiments of the present disclosure, storage resources occupied by a directory can be reduced.

Abstract: A memory access device allocate a memory resource to a node in a system to reduce maintenance overheads of the system and implement flexible scheduling of memory resources. The device includes a cloud control device on the side of a requesting node and a cloud control device on the side of a contributing node. The cloud control device on the side of the requesting node generates a request packet for accessing to-be-accessed data stored in the contributing node which provides memory resource, sends the request packet to the contributing node t. The cloud control device on the side of the contributing node receives the request packet, provides a request message to the contributing node, generates the response packet for the contributing node, and sends the response packet to the requesting node.