Abstract: A multi-sensor data fusion-based self-powered online monitoring system for a transmission line includes a plurality of detection nodes, an optical communication receiving and demodulation module, and a data processing module. The detection nodes each include a vibration energy harvesting module, a sensing module, and an optical communication modulation and transmitting module. The detection node uses a triboelectric nanogenerator (TENG) to convert and harvest energy, uses the sensing module to acquire a plurality of types of sensing data, and uses the optical communication modulation and transmitting module to modulate and transmit the sensing data. The optical communication receiving and demodulation module correspondingly receives and demodulates the sensing data, and transmits the sensing data to the data processing module for processing.

Abstract: The present application provides a data backup method and a restoration method for an NVDIMM, an NVDIMM controller and an NVDIMM. The NVDIMM (200) comprises a DRAM (201), a NAND flash memory (202) and an NVDIMM controller (100), the NVDIMM controller (100) controlling the NVDIMM (200) and comprising a DDR controller (101), a NAND flash memory controller (102), a data backup module (103) and a data restoration module (104), the DDR controller (101) using and enabling DBI mechanism. During data backup, the DDR controller (101) reads N-bit DQi and 1-bit DBI from the DRAM (201) and sends the same to the data backup module (103). When DBIi is “1”, the data backup module (103) compares the DQi and DQi-1. If the number of bits of the DQi and the DQi-1 with different values is greater than N/2, then the DQi is inverted and the DBIi is set to “0”, and otherwise the DQi and the DBIi are remained unchanged. When the DBIi is “0”, the DQi and the DBIi are remained unchanged.

Abstract: An LLC chip and a cache system are provided. The LLC chip includes a storage wafer, an interface logic unit and a packaging substrate. The interface logic unit and the storage wafer are arranged in sequence on the packaging substrate. A plurality of processing assemblies is connected to the interface logic unit so as to perform read and write operations on the storage wafer through the interface logic unit. The storage wafer includes at least one storage space. The plurality of processing assemblies performs read and write operations on a specific storage space or any storage space so as to achieve non-shared independent storage access or shared storage access. Signal transmission bandwidth is thus improved by means of the plurality of distributed interfaces, and data is cached by means of a non-shared mode or shared mode so as to increase data accessing efficiency of the processing assemblies.

Abstract: The NVDIMM (200) comprises a DRAM (201), a NAND flash memory (202) and a NVDIMM controller (100), the NVDIMM controller (100) controlling the NVDIMM (200) and comprising a DDR controller (101), a NAND flash memory controller (102), a data backup module (103) and a data recovery module (104), and the DDR controller (101) using and enabling DBI. The backup method comprises: reading, by the DDR controller (101), N-bit DQ and 1-bit DBI from the DRAM (201) and sending the same to the data backup module; encoding, by the data backup module (103), the N-bit DQ and the 1-bit DBI into N-bit EDQ according to the values of the N-bit DQ and the 1-bit DBI, and sending the N-bit EDQ to the NAND flash memory controller; and receiving, by the NAND flash memory controller (102), the N-bit EDQ and writing the N-bit EDQ into the NAND flash memory (202).

Abstract: A multi-sensor data fusion-based self-powered online monitoring system for a transmission line includes a plurality of detection nodes, an optical communication receiving and demodulation module, and a data processing module. The detection nodes each include a vibration energy harvesting module, a sensing module, and an optical communication modulation and transmitting module. The detection node uses a triboelectric nanogenerator (TENG) to convert and harvest energy, uses the sensing module to acquire a plurality of types of sensing data, and uses the optical communication modulation and transmitting module to modulate and transmit the sensing data. The optical communication receiving and demodulation module correspondingly receives and demodulates the sensing data, and transmits the sensing data to the data processing module for processing.

Abstract: Provided are a near-memory computing module and method, a near-memory computing network, and a construction method. The near-memory computing module employs a three-dimensional design, computing submodules and a memory submodule are provided in different layers, the layers are connected by means of bonding, and the total data bit width connected is a positive integer multiple of the data bit width of a single computing unit (201). Multiple memory units (203) are provided in the memory submodule, thus allowing a large memory capacity to be implemented in a single memory submodule. Computing units of the computing submodule exchange data with each other via an exchange interface of a router (202); moreover, among the computing submodules data is accessed via a routing interface. The near-memory computing network utilizes the near-memory computing module and satisfies computing requirements of different scales.

Abstract: The present application relates to an in-memory computing module and method, and an in-memory computing network and a construction method therefor. The in-memory computing module comprises at least two computing submodules, and low latency can be achieved when computing units in the computing submodules access memory units. Multiple computing submodules present a symmetric layer design, and such a symmetric layer structure facilitates the construction of a topology network so as to achieve large-scale or ultra-large-scale computation. The memory capacity of the memory units in each computing submodule can be customized, and designed flexibly. These computing submodules are in a bonding connection, and the data bit width after the bonding connection may be positive integer multiple of the data bit width of the computing units, so that high data bandwidth is achieved.

Abstract: The present application provides a data backup method and a restoration method for an NVDIMM, an NVDIMM controller and an NVDIMM. The NVDIMM (200) comprises a DRAM (201), a NAND flash memory (202) and an NVDIMM controller (100), the NVDIMM controller (100) controlling the NVDIMM (200) and comprising a DDR controller (101), a NAND flash memory controller (102), a data backup module (103) and a data restoration module (104), the DDR controller (101) using and enabling DBI mechanism. During data backup, the DDR controller (101) reads N-bit DQi and 1-bit DBI from the DRAM (201) and sends the same to the data backup module (103). When DBIi is “1”, the data backup module (103) compares the DQi and DQi-1. If the number of bits of the DQi and the DQi-1 with different values is greater than N/2, then the DQi is inverted and the DBIi is set to “0”, and otherwise the DQi and the DBIi are remained unchanged. When the DBIi is “0”, the DQi and the DBIi are remained unchanged.

Abstract: The present application provides a data backup and recovery method for an NVDIMM, an NVDIMM controller (100) and an NVDIMM (200). The NVDIMM (200) comprises a DRAM (201), a NAND flash memory (202) and a NVDIMM controller (100), the NVDIMM controller (100) controlling the NVDIMM (200) and comprising a DDR controller (101), a NAND flash memory controller (102), a data backup module (103) and a data recovery module (104), and the DDR controller (101) using and enabling DBI. The backup method comprises: reading, by the DDR controller (101), N-bit DQ and 1-bit DBI from the DRAM (201) and sending the same to the data backup module; encoding, by the data backup module (103), the N-bit DQ and the 1-bit DBI into N-bit EDQ according to the values of the N-bit DQ and the 1-bit DBI, and sending the N-bit EDQ to the NAND flash memory controller; and receiving, by the NAND flash memory controller (102), the N-bit EDQ and writing the N-bit EDQ into the NAND flash memory (202).