Abstract: In an example embodiment, the system receives user inputs including: (1) a netlist that describes the circuit elements and connections of an integrated circuit; (2) a mathematical device model that corresponds to the integrated circuit and that includes an equation with a number of parameters and decision variables grouped into terms; and (3) a description of an input voltage. Based on these inputs, the system calculates an output such as a voltage or current. The system displays a GUI that includes a view which shows each of the terms of the equation after a value has been assigned to each parameter and to each decision variable and a view which shows each of the terms of the equation after reduction of the values assigned to each parameter and each decision variable. Upon receipt of a user's change to the value of a parameter, the system promptly updates the views.

Abstract: The present invention presents methods for modeling the high frequency and noise characterization of MOSFETs. The models may be readily implemented as part of a SPICE or other simulation in a design flow. In particular, this invention is capable of providing a sub-circuit representation of a MOSFET that can accurately predicate a MOSFET's low frequency, high frequency, and noise characterizations. An interface is described through which a user may simultaneously optimize all of these characterizations. Further, methods are presented for building models that can predicate the variations in MOSFETs due to manufacturing processes and generate a corresponding corner model.

Abstract: A method for generating a layout for an analog circuit design is provided. The method includes tracing a signal flow through a circuit netlist, and partitioning the circuit netlist into a digital portion and an analog portion. A signal flow is defined through the analog portion of the circuit netlist. A system for generating a layout for an analog circuit design is also included.

Abstract: The present invention presents methods for modeling the high frequency and noise characterization of MOSFETs. The models may be readily implemented as part of a SPICE or other simulation in a design flow. In particular, this invention is capable of providing a sub-circuit representation of a MOSFET that can accurately predicate a MOSFET's low frequency, high frequency, and noise characterizations. An interface is described through which a user may simultaneously optimize all of these characterizations. Further, methods are presented for building models that can predicate the variations in MOSFETs due to manufacturing processes and generate a corresponding corner model.

Abstract: The present invention presents methods for modeling the high frequency and noise characterization of MOSFETs. The models may be readily implemented as part of a SPICE or other simulation in a design flow. In particular, this invention is capable of providing a sub-circuit representation of a MOSFET that can accurately predicate a MOSFET's low frequency, high frequency, and noise characterizations. An interface is described through which a user may simultaneously optimize all of these characterizations. Further, methods are presented for building models that can predicate the variations in MOSFETs due to manufacturing processes and generate a corresponding corner model.

Abstract: A method for generating a layout for an analog circuit design is provided. The method includes tracing a signal flow through a circuit netlist, and partitioning the circuit netlist into a digital portion and an analog portion. A signal flow is defined through the analog portion of the circuit netlist. A system for generating a layout for an analog circuit design is also included.

Abstract: The present invention presents methods for modeling the high frequency and noise characterization of MOSFETs. The models may be readily implemented as part of a SPICE or other simulation in a design flow. In particular, this invention is capable of providing a sub-circuit representation of a MOSFET that can accurately predicate a MOSFET's low frequency, high frequency, and noise characterizations. An interface is described through which a user may simultaneously optimize all of these characterizations. Further, methods are presented for building models that can predicate the variations in MOSFETs due to manufacturing processes and generate a corresponding corner model.

Abstract: The present invention presents methods for modeling the high frequency and noise characterization of MOSFETs. The models may be readily implemented as part of a SPICE or other simulation in a design flow. In particular, this invention is capable of providing a sub-circuit representation of a MOSFET that can accurately predicate a MOSFET's low frequency, high frequency, and noise characterizations. An interface is described through which a user may simultaneously optimize all of these characterizations. Further, methods are presented for building models that can predicate the variations in MOSFETs due to manufacturing processes and generate a corresponding corner model.

Abstract: An analytical parasitic constraint generation technique for parasitic loading constraints generation based on analytical assessment of circuit nodes time constants. The inventive device includes DC operating point simulation, open circuit time constant calculator, circuit bandwidth estimation, parasitic loading constraints generator. DC operating point simulation calculates the equivalent resistive impedance at each circuit node. The time constant calculator analytically assesses the time constant related to each circuit node based on open-circuit time constant technique. Circuit bandwidth estimation module estimates the bandwidth of the circuit based on the calculated time constants at each node and then compares with band-with requirement. Parasitic loading constraints generator calculates the tolerable excessive parasitic loading at each circuit node to be used in physical synthesis, or to select optimal circuit topology.

Abstract: A signal flow driven circuit analysis and partition technique are provided for mixed signal circuit performance optimization, yield enhancement and layout optimization. The inventive device includes automatic partition of mixed signal integrated circuits based on functional blocks, automatic identification of critical signal path in analog/RF circuits, automatic identification of fundamental unit circuits, automatic identification of matching and symmetry requirement. Circuit partition automatically partitions a mixed signal circuit into blocks based on their functionality. Identification of signal flow is achieved by automatically tracing the signal flow and identifies the critical path based a set of rules. Various building blocks of known characteristics and optimization requirement can also be automatically obtained. By tracing the signal path, matching and symmetry requirement and parasitic loading requirement at critical circuit nodes can also be automatically generated.

Abstract: A signal flow driven circuit physical synthesis technique for automatic generation of a high performance and compact layout from a circuit schematic based on signal flow information. The signal flow driven layout methodology is based on two observations: matching and symmetry requirement most critical with devices in the critical signal paths, parasitic reduction (mostly capacitance, resistance, and inductance if possible) is most critical with circuit nodes in the signal path. The inventive device includes input module, critical device generator, signal flow driven placement module, and parasitic aware routing module. Input module loads circuit netlist, technology files, signal flow information and parasitic constraints. Critical device generator synthesizes circuit component with optimized for matching, symmetry, area and parasitic loading. Placement module places circuit components while optimizing for those in the critical signal flow.

Abstract: The present invention includes a method for generating typical and corner device models to account for statistical variations in a semiconductor device fabrication process. The typical and corner models can be generated before the semiconductor device fabrication process is fully developed based on a process specification associated with the semiconductor device fabrication process. The typical and corner models can also be generated with better accuracy after the semiconductor device fabrication process is developed and measured data are available for model generation.

Abstract: The present invention presents methods for modeling the high frequency and noise characterization of MOSFETs. The models may be readily implemented as part of a SPICE or other simulation in a design flow. In particular, this invention is capable of providing a sub-circuit representation of a MOSFET that can accurately predicate a MOSFET's low frequency, high frequency, and noise characterizations. An interface is described through which a user may simultaneously optimize all of these characterizations. Further, methods are presented for building models that can predicate the variations in MOSFETs due to manufacturing processes and generate a corresponding corner model.

Abstract: The present invention presents methods for modeling the high frequency and noise characterization of MOSFETs. The models may be readily implemented as part of a SPICE or other simulation in a design flow. In particular, this invention is capable of providing a sub-circuit representation of a MOSFET that can accurately predicate a MOSFET's low frequency, high frequency, and noise characterizations. An interface is described through which a user may simultaneously optimize all of these characterizations. Further, methods are presented for building models that can predicate the variations in MOSFETs due to manufacturing processes and generate a corresponding corner model.

Abstract: An exemplary method for simulating the effect of mismatch in design flows comprises receiving measured data, receiving an original model, extracting a mismatch model based on the measured data and the original model, attaching the mismatch model to the netlist to obtain a modified netlist, and simulating an effect of mismatch based on the modified netlist. In one embodiment, the extracting of a mismatch model includes selecting a set of model parameters, generating a distribution of mismatch values for each of the model parameters, extracting a set of linking coefficients based on said mismatch values, and extracting said mismatch model based on said set of linking coefficients.